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s3c2400 risc microprocessor product o verview 1- 1 1 product overview introduction samsung's s3c2400 16/32-bit risc micro processor is designed to provide a cost-effective, low power, small die size and high performance micro-controller solution for hand-held devices and general applications. to reduce total system cost, s3c2400 also provides the following: separate 16kb instruction and 16kb data cache, mmu to handle virtual memory management, lcd controller (stn & tft), 2-channel uart with handshake, 4-channel dma, system manager (chip select logic, edo/sdram controller), 4-channel timers with pwm, i/o ports, rtc, 8- channel 10-bit adc, iic-bus interface, iis-bus interface, usb host, usb device, multi-media card interface, spi and pll for clock generation. the s3c2400 was developed using an arm920t core, 0.18um cmos standard cells and a memory complier. its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. also s3c2400 adopts a new bus architecture, amba (advanced microcontroller bus architecture) an outstanding feature of the s3c2400 is its cpu core, a 16/32-bit arm920t risc processor designed by advanced risc machines, ltd. the arm920t implements mmu, amba bus, and harvard cache architecture with separate 16kb instruction and 16kb data caches, each with a 8-word line length. by providing complete set of common system peripherals, the s3c2400 minimizes overall system costs and eliminates the need to configure additional components. the integrated on-chip functions that are described in this document include: 1.8v internal, 3.3v external (i/o boundary) microprocessor with 16kb i-cache, 16kb d-cache, and mmu. external memory controller. (edo/sdram control, chip select logic) lcd controller (up to 4k color stn and 64k color tft) with 1-ch lcd-dedicated dma. 4-ch dmas with external request pins 2-ch uart with handshake (irda1.0, 16-byte fifo)/1-ch spi 1-ch multi-master iic-bus/1-ch iis-bus controller mmc interface (ver 2.11) 2-port usb host /1- port usb device (ver 1.1) 4-ch pwm timers & 1-ch internal timer watch dog timer 90-bit general purpose i/o ports/8-ch external interrupt source power control: normal, slow, idle, stop and sl_idle mode 8-ch 10-bit adc. rtc with calendar function. on-chip clock generator with pll
product overview s3 c2400 risc microprocessor 1- 2 features architecture integrated system for hand-held devices and general embedded applications. 16/32-bit risc architecture and powerful instruction set with arm920t cpu core. enhanced arm architecture mmu to support wince, epoc 32 and linux. instruction cache, data cache, write buffer and physical address tag ram to reduce the effect of main memory bandwidth and latency on performance. arm920t cpu core supports the arm debug architecture and has a tracking ice mode. internal amba(advanced microcontroller bus architecture) (amba2.0, ahb/apb) system manager little/big endian support. address space: 32m bytes for each bank (total 256mbyte) supports programmable 8/16/32-bit data bus width for each bank. fixed bank start address and programmable bank size for 7 banks. programmable bank start address and bank size for one bank. 8 memory banks. ? 6 memory banks for rom, sram etc. ? 2 memory banks for rom/sram/dram(edo or synchronous dram) fully programmable access cycles for all memory banks. supports external wait signal to expend the bus cycle. supports self-refresh mode in dram/sdram for power-down. supports asymmetric/symmetric address of dram. cache memory 64 way set-associative cache with i-cache(16kb) and d-cache(16kb). 8-words per line with one valid bit and two dirty bits per line pseudo random or round robin replacement algorithm. write through or write back cache operation to update the main memory. the write buffer can hold 16 words of data and four address. clock & power manager low power the on-chip mpll and upll upll makes the clock for operating usb host/device. mpll makes the clock for operating mcu at maximum 150mhz @ 1.8v. clock can be fed selectively to each function block by software. power mode: normal, slow, idle, stop mode and sl_idle mode. normal mode: normal operating mode. slow mode: low frequency clock without pll. idle mode: stop the clock for only cpu. stop mode: all clocks are stopped. sl_idle mode: all clocks except lcd are stopped. wake up by eint[7:0] or rtc alarm interrupt from stop mode. interrupt controller 32 interrupt sources (watch dog timer, 5timer, 6uart, 8external interrupts, 4 dma, 2 rtc, 1 adc, 1 iic, 1 spi, 1 mmc, 2 usb) level/edge mode on external interrupt source. programmable polarity of edge and level. supports fiq (fast interrupt request) for very urgent interrupt request.
s3c2400 risc microprocessor product ov erview 1- 3 timer with pwm (pulse width modulation) 4-ch 16-bit timer with pwm / 1-ch 16-bit internal timer with dma-based or interrupt-based operation programmable duty cycle, frequency, and polarity dead-zone generation. supports external clock source. rtc (real time clock) full clock feature: msec, sec, min, hour, day, week, month, year. 32.768 khz operation. alarm interrupt. time tick interrupt general purpose input/output ports 8 external interrupt ports 90 multiplexed input/output ports uart 2-channel uart with dma-based or interrupt- based operation supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive supports h/w handshaking during transmit/receive programmable baud rate supports irda 1.0 loop back mode for testing each channel has internal 16-byte tx fifo and 16-byte rx fifo. dma controller 4-ch dma controller. support memory to memory, io to memory, memory to io, io to io burst transfer mode to enhance the transfer rate. a/d converter 8-ch multiplexed adc. max. 500ksps and 10-bit resolution. lcd controller stn lcd displays feature supports 3 types of stn lcd panels ; 4-bit dual scan, 4-bit single scan, 8-bit single scan display type. supports the monochrome, 4 gray levels, 16gray levels, 256 color and 4096 colors for stn lcd. supports multiple screen size ? typical actual screen size: 640x480, 320x240, 160x160 (pixels) ? maximum virtual screen size (color mode): 4096x1024, 2048x2048, 1024x4096 etc. supports power saving mode(enhanced sl_idle mode.) tft (thin film transistor) color displays feature supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color tft. supports 16 bpp non-palette true-color displays for color tft. supports maximum 32k (64k using intensity) color tft at 16 bpp mode. supports multiple screen size ? typical actual screen size: 720x240, 320x240, 160x160 (pixels) ? recommended maximum screen size: 640x480 (8 bpp, 32bit sdram @80mhz) ? maximum virtual screen size (16bpp mode): 2048x1024 etc watchdog timer 16-bit watchdog timer. interrupt request or system reset at time-out.
product overview s3 c2400 risc microprocessor 1- 4 iic-bus interface 1-ch multi-master iic-bus. serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 kbit/s in the standard mode or up to 400 kbit/s in the fast mode. iis-bus interface 1-ch iis-bus for audio interface with dma-based operation. serial, 8/16bit per channel data transfers. supports iis format and msb-justified data format. usb host 2-port usb host complies with ohci rev. 1.0 compatible with the usb specification version 1.1 usb device 1-port usb device. 5 endpoints for usb device. compatible with the usb specification version 1.1 mmc interface multi-media card protocol version 2.11 compatible 2x16 bytes fifo for receive/transmit. dma-based or interrupt-based operation. spi interface serial peripheral interface protocol version 2.11 compatible 2x8 bits shift register for receive/transmit. dma-based or interrupt-based operation. operating voltage range core: 1.8v i/o: 3.3v operating frequency up to 150 mhz package 208 lqfp/208 fbga
s3c2400 risc microprocessor product ov erview 1- 5 block diagram arm920t arm9tdmi processor core (internal embedded ice) dd[31:0] writeback pa tag ram data mmu c13 dva[31:0] dv 2 a[31:0] instructionca che (16kb) instruction mmu external coproc interface c13 id[31:0] ipa[31:0] iv 2 a[31:0] cp15 write buffer amba bus i/f jtag data cache (16kb) wbpa[31:0] dpa[31:0] bridge & dma(4ch) clock generator ( m pll) a h b b u s memory cont. sram/rom/dram/sdram bus cont. arbitor/decode power management interrupt cont. usb host cont. extmaster lcd dma lcd cont. a p b b u s i2c gpio i2s rtc spi adc uart 0, 1 mmc usb device watchdog timer bus cont. arbitor/decode timer/pwm 0 ~ 3, 4(internal) figure 1-1. s3c2400 block diagram
product overview s3 c2400 risc microprocessor 1- 6 pin assignments upllcap vddi_mpll vssi_mpll mpllcap vddi_upll vssi_upll 120 119 118 117 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 vddi extclk vssio xtopll xtipll vddio vddi sclk ngcs5/gpa17 ngcs6:nscs0:nras0 ngcs7:nscs1:nras1 nwait/gpd10 scke/gpa10 vssi ngcs4/gpa16 ngcs3/gpa15 ngcs2/gpa14 vssio ngcs1/gpa13 ngcs0 nwe vddio nbe0:nwbe0:dqm0 nbe3:nwbe3:dqm3 nbe2:nwbe2:dqm2 nbe1:nwbe1:dqm1 ncas3:nsras noe n.c 121 122 123 124 125 126 127 128 eint0/gpe0 eint1/gpe1/nss eint2/gpe2/i2ssdi eint3/gpe3/ncts1 eint4/gpe4/nrts1 eint5/gpe5/tclk1 eint6/gpe6 eint7/gpe7 nreset 105 106 107 108 109 110 111 112 113 114 115 116 53 54 55 56 57 58 60 59 65 64 63 62 61 68 67 66 74 73 72 71 70 69 76 77 78 79 80 75 86 85 84 83 82 81 88 89 90 91 92 87 mmcdat/gpg6/iicscl mmccmd/gpg5/iicsda 41 42 43 44 45 46 47 48 49 50 51 52 vddi vssi i2ssclk/gpg1 cdclk/gpg2 i2ssdo/gpg3/i2ssdi mmcclk/gpg4/i2ssdi spiclk/gpg9/mmcclk spimiso/gpg7/iicsda spimosi/gpg8/iicscl vddio vssio lend/gpd4 vclk/gpd3 vline/gpd2 vm/gpd1 vssi vddi vframe/gpd0 vd0/gpc0 vd1/gpc1 vd4/gpc4 vssio vd3/gpc3 vd2/gpc2 vd5/gpc5 vd6/gpc6 vd7/gpc7 vd8/gpc8 vd9/gpc9 vd10/gpc10 vssi vddi vd11/gpc11 vd12/gpc12 vd13/gpc13 vddio vssio vd14/gpc14 S3C2400X01 208-lqfp 1 vssio data14 data15 data16/gpb0/nxback data17/gpb1/nxbreq data18/gpb2/tclk1 data19/gpb3/txd1 data20/gpb4/rxd1 data21/gpb5/ncts1 data22/gpb6/nrts1 data29/gpb13 data28/gpb12 vssio data23/gpb7 data24/gpb8 data25/gpb9/i2ssdi data26/gpb10/nss data27/gpb11 data30/gpb14 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 data31/gpb15 vddio vssio vssi vddi clkout/gpf6 ntrst tms tck addr13 addr16/gpa1 addr17/gpa2 addr18/gpa3 addr19/gpa4 addr20/gpa5 addr21/gpa6 addr22/gpa7 addr23/gpa8 vddio vssio addr24/gpa9 data0 data2 vddio vssi data12 data11 data13 data9 data6 data4 vddi data1 data3 data5 data7 data8 data10 tout3/gpd8 tclk0/gpd9 29 30 31 32 33 34 35 36 37 38 39 40 tdi tdo tout0/gpd5 tout1/gpd6 tout2/gpd7 nxdack1/gpe9/nxback nxdreq1/gpe11/nxbreq nxdack0/gpe8 nxdreq0/gpe10 i2slrck/gpg0 169 170 171 172 173 174 175 176 177 178 179 180 addr8 addr9 addr10 addr11 vddio vssio vddi vssi addr12 addr14 addr15 vd15/gpc15 dp1/pdp0 dn1/pdn0 dp0 dn0 vssi vddi ncts0/gpf5/nxbreq nrts0/gpf4/nxback txd0/gpf2 rxd0/gpf0 txd1/gpf3/iicscl 157 158 159 160 161 162 163 164 165 166 167 168 vssio ncas2:nscas ncas1/gpa12 ncas0/gpa11 addr0/gpa0 addr1 addr2 addr3 addr4 addr6 addr7 ain4 ain5 ain6 ain7 vdda_adc rxd1/gpf1/iicsda om3 om2 om1 om0 vssio vssa_adc avref ain0 ain1 ain2 ain3 98 97 96 95 94 93 100 101 102 103 104 99 addr5 xtirtc rtcvdd xtortc figure 1-2. s3c2400 pin assignments (208-lqfp)
s3c2400 risc microprocessor product ov erview 1- 7 l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bottom view ball pad a1 corner indicator (no soldeer ball) p n m 15 16 t r figure 1-3. s3c2400 pin assignments (208-fbga)
product overview s3 c2400 risc microprocessor 1- 8 table 1-1. 208-pin lqfp pin assignment pin number pin name default function i/o state @bus req. i/o state @stop i/o state @ nreset i/o type 1 vssio vssio ? ? p vss3op 2 data14 data14 hi-z hi-z i phbsu50ct12sm 3 data15 data15 hi-z hi-z i phbsu50ct12sm 4 data16/gpb0/nxback data16 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 5 data17/gpb1/nxbreq data17 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 6 data18/gpb2/tclk1 data18 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 7 data19/gpb3/txd1 data19 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 8 data20/gpb4/rxd1 data20 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 9 data21/gpb5/ncts1 data21 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 10 data22/gpb6/nrts1 data22 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 11 vssio vssio ? ? p vss3op 12 data23/gpb7 data23 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 13 data24/gpb8 data24 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 14 data25/gpb9/i2ssdi data25 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 15 data26/gpb10/nss data26 hi-z/ ? / ? hi-z/ ? / ? i phbsu50ct12sm 16 data27/gpb11 data27 hi-z/ ? hi-z/ ? i phbsu50ct12sm 17 data28/gpb12 data28 hi-z/ ? hi-z/ ? i phbsu50ct12sm 18 data29/gpb13 data29 hi-z/ ? hi-z/ ? i phbsu50ct12sm 19 data30/gpb14 data30 hi-z/ ? hi-z/ ? i phbsu50ct12sm 20 data31/gpb15 data31 hi-z/ ? hi-z/ ? i phbsu50ct12sm 21 vddio vddio ? ? p vdd3op 22 vssio vssio ? ? p vss3op 23 vssi vssi ? ? p vss3i 24 vddi vddi ? ? p vdd1ih_core 25 clkout/gpf6 gpf6 ? / ? -/- i phbsu50ct8sm 26 ntrst ntrst ? ? i phic 27 tms tms ? ? i phic 28 tck tck ? ? i phic 29 tdi tdi ? ? i phic 30 tdo tdo ? ? o phot8 31 tout0/gpd5 gpd5 ? / ? ? / ? i phbsu50ct8sm 32 tout1/gpd6 gpd6 ? / ? ? / ? i phbsu50ct8sm 33 tout2/gpd7 gpd7 ? / ? / ? ? / ? / ? i phbsu50ct8sm
s3c2400 risc microprocessor product ov erview 1- 9 table 1-1. 208-pin lqfp pin assignment (continued) pin number pin name default function i/o state @bus req. i/o state @stop i/o state @ nreset i/o type 34 tout3/gpd8 gpd8 ? / ? / ? ? / ? / ? i phbsu50ct8sm 35 tclk0/gpd9 gpd9 ? / ? ? / ? i phbsu50ct8sm 36 nxdack1/gpe9/ nxback gpe9 ? / ? / ? ? / ? / ? i phbsu50ct8sm 37 nxdreq1/gpe11/ nxbreq gpe11 ? / ? / ? ? / ? / ? i phbsu50ct8sm 38 nxdack0/gpe8 gpe8 ? / ? ? / ? i phbsu50ct8sm 39 nxdreq0/gpe10 gpe10 ? / ? ? / ? i phbsu50ct8sm 40 i2slrck/gpg0 gpg0 ? / ? ? / ? i phbsu50ct8sm 41 vddi vddi ? ? p vdd1ih_core 42 vssi vssi ? ? p vss3i 43 i2ssclk/gpg1 gpg1 ? / ? ? / ? i phbsu50ct8sm 44 cdclk/gpg2 gpg2 ? / ? ? / ? i phbsu50ct8sm 45 i2ssdo/gpg3/i2ssdi gpg3 ? / ? / ? ? / ? / ? i phbsu50ct8sm 46 mmcdat/gpg6/iicscl gpg6 ? / ? / ? ? / ? / ? i phbsu50cdct8sm 47 mmccmd/gpg5/ iicsda gpg5 ? / ? / ? ? / ? / ? i phbsu50cdct8sm 48 mmcclk/gpg4/i2ssdi gpg4 ? / ? / ? ? / ? / ? i phbsu50ct8sm 49 spiclk/gpg9/ mmcclk gpg9 ? / ? / ? ? / ? / ? i phbsu50ct8sm 50 spimiso/gpg7/iicsda gpg7 ? / ? / ? ? / ? / ? i phbsu50cdct8sm 51 spimosi/gpg8/iicscl gpg8 ? / ? / ? ? / ? / ? i phbsu50cdct8sm 52 vddio vddio ? ? p vdd3op 53 vssio vssio ? ? p vss3op 54 lend/gpd4 gpd4 ? / ? ? / ? i phbsu50ct8sm 55 vclk/gpd3 gpd3 ? / ? ? / ? i phbsu50ct8sm 56 vline:hsync/gpd2 gpd2 ? : ? / ? ? : ? / ? i phbsu50ct8sm 57 vm:vden/gpd1 gpd1 ? : ? / ? ? : ? / ? i phbsu50ct8sm 58 vssi vssi ? ? p vss3i 59 vddi vddi ? ? p vdd1ih_core 60 vframe:vsync/gpd0 gpd0 ? : ? / ? ? : ? / ? i phbsu50ct8sm 61 vd0/gpc0 gpc0 ? / ? ? / ? i phbsu50ct8sm 62 vd1/gpc1 gpc1 ? / ? ? / ? i phbsu50ct8sm 63 vd2/gpc2 gpc2 ? / ? ? / ? i phbsu50ct8sm 64 vd3/gpc3 gpc3 ? / ? ? / ? i phbsu50ct8sm
product overview s3 c2400 risc microprocessor 1- 10 65 vssio vssio ? ? p vss3op
s3c2400 risc microprocessor product ov erview 1- 11 table 1-1. 208-pin lqfp pin assignment (continued) pin number pin name default function i/o state @bus req. i/o state @stop i/o state @ nreset i/o type 66 vd4/gpc4 gpc4 ? / ? ? / ? i phbsu50ct8sm 67 vd5/gpc5 gpc5 ? / ? ? / ? i phbsu50ct8sm 68 vd6/gpc6 gpc6 ? / ? ? / ? i phbsu50ct8sm 69 vd7/gpc7 gpc7 ? / ? ? / ? i phbsu50ct8sm 70 vd8/gpc8 gpc8 ? / ? ? / ? i phbsu50ct8sm 71 vd9/gpc9 gpc9 ? / ? ? / ? i phbsu50ct8sm 72 vd10/gpc10 gpc10 ? / ? ? / ? i phbsu50ct8sm 73 vssi vssi ? ? p vss3i 74 vddi vddi ? ? p vdd1ih_core 75 vd11/gpc11 gpc11 ? / ? ? / ? i phbsu50ct8sm 76 vd12/gpc12 gpc12 ? / ? ? / ? i phbsu50ct8sm 77 vd13/gpc13 gpc13 ? / ? ? / ? i phbsu50ct8sm 78 vddio vddio ? ? p vdd3op 79 vssio vssio ? ? p vss3op 80 vd14/gpc14 gpc14 ? / ? ? / ? i phbsu50ct8sm 81 vd15/gpc15 gpc15 ? / ? ? / ? i phbsu50ct8sm 82 dp1/pdp0 pdp0 ? / ? ? / ? ai pbusb 83 dn1/pdn0 pdn0 ? / ? ? / ? ai pbusb 84 dp0 dp0 ? ? ai pbusb 85 dn0 dn0 ? ? ai pbusb 86 vssi vssi ? ? p vss3i 87 vddi vddi ? ? p vdd1ih_core 88 ncts0/gpf5/nxbreq gpf5 ? / ? / ? ? / ? / ? i phbsu50ct8sm 89 nrts0/gpf4/nxback gpf4 ? / ? / ? ? / ? / ? i phbsu50ct8sm 90 txd0/gpf2 gpf2 ? / ? ? / ? i phbsu50ct8sm 91 rxd0/gpf0 gpf0 ? / ? ? / ? i phbsu50ct8sm 92 txd1/gpf3/iicscl gpf3 ? / ? / ? ? / ? / ? i phbsu50cdct8sm 93 rxd1/gpf1/iicsda gpf1 ? / ? / ? ? / ? / ? i phbsu50cdct8sm 94 om3 om3 ? ? i phic 95 om2 om2 ? ? i phic 96 om1 om1 ? ? i phic 97 om0 om0 ? ? i phic 98 vssio vssio ? ? p vss3op 99 vssa_adc vssa_adc ? ? p vss3t_abb
product overview s3 c2400 risc microprocessor 1- 12 table 1-1. 208-pin lqfp pin assignment (continued) pin number pin name default function i/o state @bus req. i/o state @stop i/o state @ nreset i/o type 100 avref avref ? ? ai phia_abb 101 ain0 ain0 ? ? ai phia_abb 102 ain1 ain1 ? ? ai phia_abb 103 ain2 ain2 ? ? ai phia_abb 104 ain3 ain3 ? ? ai phia_abb 105 ain4 ain4 ? ? ai phia_abb 106 ain5 ain5 ? ? ai phia_abb 107 ain6 ain6 ? ? ai phia_abb 108 ain7 ain7 ? ? ai phia_abb 109 vdda_adc vdda_adc ? ? p vdd3t_abb 110 xtortc xtortc ? ? ao phgpad_option 111 xtirtc xtirtc ? ? ai phgpad_option 112 rtcvdd rtcvdd ? ? p vdd1ih 113 vddi_mpll vddi_mpll ? ? p vdd1ih_core 114 vssi_mpll vssi_mpll ? ? p vss3i 115 mpllcap mpllcap ? ? ai phgpad_option 116 vddi_upll vddi_upll ? ? p vdd1ih_core 117 vssi_upll vssi_upll ? ? p vss3i 118 upllcap upllcap ? ? ai phgpad_option 119 eint0/gpe0 gpe0 ? / ? ? / ? i phbsu50ct8sm 120 eint1/gpe1/nss gpe1 ? / ? / ? ? / ? / ? i phbsu50ct8sm 121 eint2/gpe2/i2ssdi gpe2 ? / ? / ? ? / ? / ? i phbsu50ct8sm 122 eint3/gpe3/ncts1 gpe3 ? / ? / ? ? / ? / ? i phbsu50ct8sm 123 eint4/gpe4/nrts1 gpe4 ? / ? / ? ? / ? / ? i phbsu50ct8sm 124 eint5/gpe5/tclk1 gpe5 ? / ? / ? ? / ? / ? i phbsu50ct8sm 125 eint6/gpe6 gpe6 ? / ? / ? ? / ? / ? i phbsu50ct8sm 126 eint7/gpe7 gpe7 ? / ? / ? ? / ? / ? i phbsu50ct8sm 127 n.c ? ? ? ? 128 nreset nreset ? ? i phis 129 vddi vddi ? ? p vdd1ih 130 extclk extclk ? ? i phic 131 vssio vssio ? ? p vss3op 132 xtopll xtopll ? ? ao phsoscm26
s3c2400 risc microprocessor product ov erview 1- 13 table 1-1. 208-pin lqfp pin assignment (continued) pin number pin name default function i/o state @bus req. i/o state @stop i/o state @ nreset i/o type 133 xtipll xtipll ? ? ai phsoscm26 134 vddio vddio ? ? p vdd3op 135 vddi vddi ? ? p vdd1ih_core 136 sclk sclk hi-z low o(sclk) phot12sm 137 vssi vssi ? ? p vss3i 138 scke/gpa10 scke hi-z/o low/o o(h) phot8 139 nwait/gpd10 gpd10 ? / ? ? / ? i phbsu50ct8sm 140 ngcs7:nscs1:nras1 ngcs7 hi-z:hi-z:hi-z high:high:low o(h) phot8 141 ngcs6:nscs0:nras0 ngcs6 hi-z:hi-z:hi-z high:high:low o(h) phot8 142 ngcs5/gpa17 ngcs5 hi-z/o hi-z or pre/o o(h) phot8 143 ngcs4/gpa16 ngcs4 hi-z/o hi-z or pre/o o(h) phot8 144 ngcs3/gpa15 ngcs3 hi-z/o hi-z or pre/o o(h) phot8 145 ngcs2/gpa14 ngcs2 hi-z/o hi-z or pre/o o(h) phot8 146 vssio vssio ? ? p vss3op 147 ngcs1/gpa13 ngcs1 hi-z/o hi-z or pre/o o(h) phot8 148 ngcs0 ngcs0 hi-z hi-z or pre o(h) phot8 149 nwe nwe hi-z hi-z or pre o(h) phot8 150 noe noe hi-z hi-z or pre o(h) phot8 151 nbe0:nwbe0:dqm0 dqm0 hi-z:hi-z:hi-z hi-z or pre: hi-z or pre: hi-z or pre o(h) phot8 152 nbe1:nwbe1:dqm1 dqm1 hi-z:hi-z:hi-z hi-z or pre: hi-z or pre: hi-z or pre o(h) phot8 153 nbe2:nwbe2:dqm2 dqm2 hi-z:hi-z:hi-z hi-z or pre: hi-z or pre: hi-z or pre o(h) phot8 154 nbe3:nwbe3:dqm3 dqm3 hi-z:hi-z:hi-z hi-z or pre: hi-z or pre: hi-z or pre o(h) phot8 155 ncas3:nsras nsras hi- z:hi-z low:high o(h) phot8 156 vddio vddio ? ? p vdd3op 157 vssio vssio ? ? p vss3op
product overview s3 c2400 risc microprocessor 1- 14 table 1-1. 208-pin lqfp pin assignment (continued) pin number pin name default function i/o state @bus req. i/o state @stop i/o state @ nreset i/o type 158 ncas2:nscas nscas hi- z:hi-z low:high o(h) phot8 159 ncas1/gpa12 ncas1 hi-z/o low/o o(h) phot8 160 ncas0/gpa11 ncas0 hi-z/o low/o o(h) phot8 161 addr0/gpa0 addr0 hi-z/o hi-z or pre/o o(l) phot8 162 addr1 addr1 hi-z hi-z or pre o(l) phot8 163 addr2 addr2 hi-z hi-z or pre o(l) phot8 164 addr3 addr3 hi-z hi-z or pre o(l) phot8 165 addr4 addr4 hi-z hi-z or pre o(l) phot8 166 addr5 addr5 hi-z hi-z or pre o(l) phot8 167 addr6 addr6 hi-z hi-z or pre o(l) phot8 168 addr7 addr7 hi-z hi-z or pre o(l) phot8 169 addr8 addr8 hi-z hi-z or pre o(l) phot8 170 addr9 addr9 hi-z hi-z or pre o(l) phot8 171 addr10 addr10 hi-z hi-z or pre o(l) phot8 172 addr11 addr11 hi-z hi-z or pre o(l) phot8 173 vddio vddio ? ? p vdd3op 174 vssio vssio ? ? p vss3op 175 vddi vddi ? ? p vdd1ih_core 176 vssi vssi ? ? p vss3i 177 addr12 addr12 hi-z hi-z or pre o(l) phot8 178 addr13 addr13 hi-z hi-z or pre o(l) phot8 179 addr14 addr14 hi-z hi-z or pre o(l) phot8 180 addr15 addr15 hi-z hi-z or pre o(l) phot8 181 addr16/gpa1 addr16 hi-z/o hi-z or pre/o o(l) phot8 182 addr17/gpa2 addr17 hi-z/o hi-z or pre/o o(l) phot8 183 addr18/gpa3 addr18 hi-z/o hi-z or pre/o o(l) phot8 184 addr19/gpa4 addr19 hi-z/o hi-z or pre/o o(l) phot8 185 addr20/gpa5 addr20 hi-z/o hi-z or pre/o o(l) phot8 186 addr21/gpa6 addr21 hi-z/o hi-z or pre/o o(l) phot8 187 addr22/gpa7 addr22 hi-z/o hi-z or pre/o o(l) phot8 188 addr23/gpa8 addr23 hi-z/o hi-z or pre/o o(l) phot8 189 vddio vddio ? ? p vdd3op 190 vssio vssio ? ? p vss3op
s3c2400 risc microprocessor product ov erview 1- 15 table 1-1. 208-pin lqfp pin assignment (continued) pin number pin name default function i/o state @bus req. i/o state @stop i/o state @ nreset i/o type 191 addr24/gpa9 addr24 hi-z/o hi-z or pre/o o(l) phot8 192 data0 data0 hi-z hi-z i phbsu50ct12sm 193 data1 data1 hi-z hi-z i phbsu50ct12sm 194 data2 data2 hi-z hi-z i phbsu50ct12sm 195 data3 data3 hi-z hi-z i phbsu50ct12sm 196 data4 data4 hi-z hi-z i phbsu50ct12sm 197 data5 data5 hi-z hi-z i phbsu50ct12sm 198 data6 data6 hi-z hi-z i phbsu50ct12sm 199 data7 data7 hi-z hi-z i phbsu50ct12sm 200 vddi vddi ? ? p vdd1ih_core 201 vssi vssi ? ? p vss3i 202 data8 data8 hi-z hi-z i phbsu50ct12sm 203 data9 data9 hi-z hi-z i phbsu50ct12sm 204 data10 data10 hi-z hi-z i phbsu50ct12sm 205 data11 data11 hi-z hi-z i phbsu50ct12sm 206 data12 data12 hi-z hi-z i phbsu50ct12sm 207 data13 data13 hi-z hi-z i phbsu50ct12sm 208 vddio vddio ? ? p vdd3op notes: 1. the @bus req. shows the pin states at the external bus, which is used by the other bus mast er. the @stop shows the pin states when s3c2400 is in stop mode. 2. ' ? ? mark indicates the unchanged pin state at stop mode or bus request mode. 3. hi-z or pre means hi-z or previous state and which is determined by the setting of misccr register. 4. ai/ao means analog input/output. 5. p, i, and o mean power, input and output respectively. 6. the i/o state @ nreset shows the pin status in the below @ nreset duration. nreset fclk @nreset 4fclk
product overview s3 c2400 risc microprocessor 1- 16 7. the below table shows the i/o types and description s. i/o type descriptions vdd1ih, vss3i 1.8v vdd/ vss for internal logic vdd1ih_core, vss3i 1.8v vdd/ vss for internal logic without input driver vdd3op, vss3op 3.3v vdd/ vss for external logic vdd3t_abb, vss3t_abb 3.3v vdd/ vss for analog circuitry phic input pad, lvcmos level phis input pad, lvcmos schmitt-trigger level pbusb usb pad phot8 output pad, tri-state, io=8ma phob8sm output pad, medium slew rate, io=8ma phot12sm output pad, tri-state, medium slew rate, io=12ma phia_abb bi-directional analog pad phgpad_option pad for analog pin phsoscm26 oscillator cell with enable and feedback resistor phbsu50ct8sm bi-directional pad, lvcmos schmit-trigger, 50kohm pull-up resistor with control, tri-state, io=8ma phbsu50ct12sm bi-directional pad, lvcmos schmit-trigger, 50kohm pull-up resistor with control, tri-state, io=12ma phbsu50cdct8sm bi-directional pad, lvcmos schmit-trigger, 50kohm pull-up resistor with control, tri-state, selectable output pad(open-drain or tri-state), io=8ma
s3c2400 risc microprocessor product ov erview 1- 17 table 1-2. 208-pin fbga pin assignment pin number pin name pin number pin name a1 vssio c1 data20/gpb4/rxd1 a2 data12 c2 data19/gpb3/txd1 a3 data9 c3 data15 a4 data8 c4 data13 a5 data6 c5 data11 a6 data2 c6 data7 a7 vssio c7 data1 a8 addr21/gpa6 c8 addr23/gpa8 a9 addr17/gpa2 c9 addr19/gpa4 a10 addr13 c10 addr15 a11 vddi c11 vssio a12 addr10 c12 addr9 a13 addr6 c13 addr4 a14 addr3 c14 ncas1/gpa12 a15 addr1 c15 vddio a16 addr0/gpa0 c16 ncas3:nsras b1 data17/gpb1/nxbreq d1 data23/gpb7 b2 data14 d2 vssio b3 vddio d3 data21/gpb5/ncts1 b4 data10 d4 data18/gpb2/tclk1 b5 vddi d5 data16/gpb0/nxback b6 data3 d6 vssi b7 data0 d7 data4 b8 addr22/gpa7 d8 vddio b9 addr18/gpa3 d9 addr20/gpa5 b10 addr14 d10 addr12 b11 vssi d11 vddio b12 addr11 d12 addr5 b13 addr7 d13 vssio b14 addr2 d14 nbe3:nwbe3:dqm3 b15 ncas0/gpa11 d15 nbe2:nwbe2:dqm2 b16 ncas2:nscas d16 nbe1:nwbe1:dqm1
product overview s3 c2400 risc microprocessor 1- 18 table 1-2. 208-pin fbga pin assignment (continued) pin number pin name pin number pin name e1 data25/gpb9/i2ssdi h1 ntrst e2 data26/gpb10/nss h2 tms e3 data24/gpb8 h3 tck e4 data22/gpb6/nrts1 h4 tdi e7 data5 h5 clkout/gpf6 e8 addr24/gpa9 h12 scke/gpa10 e9 addr16/gpa1 h13 vddio e10 addr8 h14 vddi e13 nbe0:nwbe0:dqm0 h15 sclk e14 noe h16 vssi e15 nwe j1 tdo e16 ngcs0 j2 tout0/gpd5 f1 data29/gpb13 j3 tout1/gpd6 f2 data30/gpb14 j4 tout2/gpd7 f3 data31/gpb15 j5 i2slrck/gpg0 f4 data27/gpb11 j12 eint7/gpe7 f13 ngcs1/gpa13 j13 extclk f14 ngcs4/gpa16 j14 vssio f15 ngcs3/gpa15 j15 xtopll f16 ngcs2/gpa14 j16 xtipll g1 vssio k1 tout3/gpd8 g2 vssi k2 tclk0/gpd9 g3 vddi k3 nxdack1/gpe9/nxback g4 vddio k4 nxdreq1/gpe11/nxbreq g5 data28/gpb12 k5 i2ssclk/gpg1 g12 vssio k12 eint0/gpe0 g13 ngcs5/gpa17 k13 eint3/gpe3/ncts1 g14 nwait/gpd10 k14 n.c g15 ngcs7:nscs1:nras1 k15 nreset g16 ngcs6:nscs0:nras0 k16 vddi
s3c2400 risc microprocessor product ov erview 1- 19 table 1-2. 208-pin fbga pin assignment(continued) pin number pin name pin number pin name l1 nxdack0/gpe8 n1 mmcdat/gpg6/iicscl l2 nxdreq0/gpe10 n2 mmcclk/gpg4/i2ssdi l3 vddi n3 spimosi/gpg8/iicscl l4 i2ssdo/gpg3/i2ssdi n4 vm:vden/gpd1 l13 upllcap n5 vd0/gpc0 l14 eint4/gpe4/nrts1 n6 vd7/ gpc7 l15 eint5/gpe5/tclk1 n7 vssi l16 eint6/gpe6 n8 vddio m1 vssi n9 dn0 m2 cdclk/gpg2 n10 rxd0/gpf0 m3 mmccmd/gpg5/iicsda n11 vssa_adc m4 spimiso/gpg7/iicsda n12 ain2 m7 vd4/gpc4 n13 vdda_adc m8 vd13/ gpc13 n14 vssi_mpll m9 nrts0/gpf4/nxback n15 mpllcap m10 om2 n16 vssi_upll m13 rtcvdd p1 spiclk/gpg9/mmcclk m14 vddi_upll p2 vddio m15 eint1/gpe1/nss p3 lend/gpd4 m16 eint2/gpe2/i2ssdi p4 vssi p5 vd3/gpc3 p6 vd8/ gpc8 p7 vddi p8 vd15/ gpc15 p9 dp0 p10 ncts0/gpf5/nxbreq p11 rxd1/gpf1/iicsda p12 om0 p13 ain1 p14 ain7 p15 xtirtc p16 vddi_mpll
product overview s3 c2400 risc microprocessor 1- 20 table 1-2. 208-pin fbga pin assignment (continued) pin number pin name pin number pin name r1 vssio t1 vline:hsync/gpd2 r2 vclk/gpd3 t2 vddi r3 vframe:vsync/gpd0 t3 vd1/gpc1 r4 vd2/gpc2 t4 vssio r5 vd5/ gpc5 t5 vd6/ gpc6 r6 vd9/ gpc9 t6 vd10/ gpc10 r7 vd12/ gpc12 t7 vd11/ gpc11 r8 vd14/ gpc14 t8 vssio r9 dn1/pdn0 t9 dp1/pdp0 r10 vddi t10 vssi r11 txd1/gpf3/iicscl t11 txd0/gpf2 r12 om1 t12 om3 r13 avref t13 vssio r14 ain4 t14 ain0 r15 ain6 t15 ain3 r16 xtortc t16 ain5
s3c2400 risc microprocessor product ov erview 1- 21 signal descriptions table 1-3. s3c2400 signal descriptions signal i/o description bus controller om[1:0] i om[1:0] sets s3c2400 in the test mode, which is used only at fabrication. also, it determines the bus width of ngcs0. the logic level is determined by the pull-up/down resistor during the reset cycle. 00:8-bit 01:16-bit 10:32-bit 11:test mode addr[24:0] o addr[24:0] (address bus) outputs the memory address of the corresponding bank . data[31:0] io data[31:0] (data bus) inputs data during memory read and outputs data during memory write. the bus width is programmable among 8/16/32-bit. ngcs[7:0] o ngcs[7:0] (general chip select) are activated when the address of a memory is within the address region of each bank. the number of access cycles and the bank size can be programmed. nwe o nwe (write enable) indicates that the current bus cycle is a write cycle. nwbe[3:0] o write byte enable nbe[3:0] o upper byte/lower byte enable(in case of sram) noe o noe (output enable) indicates that the current bus cycle is a read cycle. nxbreq i nxbreq (bus hold request) allows another bus master to request control of the local bus. back active indicates that bus control has been granted. nxback o nxback (bus hold acknowledge) indicates that the s3c2400 has surrendered control of the local bus to another bus master. nwait i nwait requests to prolong a current bus cycle. as long as nwait is l, the current bus cycle cannot be completed. dram/sdram/sram nras[1:0] o row address strobe ncas[3:0] o column address strobe nsras o sdram row address strobe nscas o sdram column address strobe nscs[1:0] o sdram chip select dqm[3:0] o sdram data mask sclk o sdram clock scke o sdram clock enable nbe[3:0] o 16-bit sram byte enable
product overview s3 c2400 risc microprocessor 1- 22 table 1-3. s3c2400 signal descriptions (continued) signal i/o description lcd control unit vd[15:0] o stn/tft: lcd data bus vclk o stn/tft: lcd clock signal vframe o stn: lcd frame signal vline o stn: lcd line signal vm o stn: vm alternates the polarity of the row and column voltage vsync o tft: vertical synchronous signal hsync o tft: horizontal synchronous signal vden o tft: data enable signal lend o tft: line end signal interrupt control unit eint[7:0] i external interrupt request dma nxdreq[1:0] i external dma request nxdack[1:0] o external dma acknowledge uart rxd[1:0] i uart receives data input txd[1:0] o uart transmits data output ncts[1:0] i uart clear to send input signal nrts[1:0] o uart request to send output signal iic-bus iicsda io iic-bus data iicscl io iic-bus clock iis-bus i2slrck io iis-bus channel select clock i2ssdo o iis-bus serial data output i2ssdi i iis-bus serial data input i2ssclk io iis-bus serial clock cdclk o codec system clock
s3c2400 risc microprocessor product ov erview 1- 23 table 1-3. s3c2400 signal descriptions (continued) signal i/o description adc ain[7:0] ai adc input[7:0] avref ai adc vref usb host dn[1:0] io data - from usb host dp[1:0] io data + from usb host usb device pdn0 io data - for usb peripheral pdp0 io data + for usb peripheral spi spimiso io spimiso is the master data input line, when spi is configured as a master. when spi is configured as a slave, this pin reverse its role. spimosi io spimosi is the master data output line, when spi is configured as a master. when spi is configured as a slave, this pin reverse its role. spiclk io spi clock nss io spi chip select when spi is configured as a master and enmul is set, nss is a slave select. when spi is configured as a slave, nss is also a slave select. mmc mmcdat io mmc receive/transmit data mmccmd io mmc receive/transmit command mmcclk o mmc clock general port gpn[89:0] io general input/output ports (some ports are output mode only) timmer/pwm tout[3:0] o timer output[3:0] tclk[1:0] i external clock input
product overview s3 c2400 risc microprocessor 1- 24 table 1-3. s3c2400 signal descriptions (continued) signal i/o description jtag test logic ntrst i ntrst(tap controller reset) resets the tap controller at start. if debugger is used, a 10k pull-up resistor has to be connected. if debugger(black ice) is not used, ntrst pin must be at l or low active pulse. tms i tms (tap controller mode select) controls the sequence of the tap controller's states. a 10k pull-up resistor has to be connected to tms pin. tck i tck (tap controller clock) provides the clock input for the jtag logic. a 10k pull-up resistor must be connected to tck pin. tdi i tdi (tap controller data input) is the serial input for test instructions and data. a 10k pull-up resistor must be connected to tdi pin. tdo o tdo (tap controller data output) is the serial output for test instructions and data. reset & clock & power nreset st nreset suspends any operation in progress and places s3c2400 into a known reset state. for a reset, nreset must be held to l level for at least 4 fclk after the processor power has been stabilized. om[3:2] i om[3:2] determines how the clock is made. om[3:2] = 00b, crystal is used for mpll clk source and upll clk source. om[3:2] = 01b, crystal is used for mpll clk source and extclk is used for upll clk source. om[3:2] = 10b, extclk is used for mpll clk source and crystal is used for upll clk source. om[3:2] = 11b, extclk is used for mpll clk source and upll clk source. extclk i external clock source. when om[3:2] = 11b, extclk is used for mpll clk source and upll clk source. when om[3:2] = 10b, extclk is used for mpll clk source only. when om[3:2] = 01b, extclk is used for upll clk source only. if it isn't used, it has to be h (3.3v). xtipll ai crystal input for internal osc circuit. when om[3:2] = 00b, xtipll is used for mpll clk source and upll clk source. when om[3:2] = 01b, xtipll is used for mpll clk source only. when om[3:2] = 10b, xtipll is used for upll clk source only. if it isn't used, xtipll has to be h (3.3v). xtopll ao crystal output for internal osc circuit. when om[3:2] = 00b, xtipll is used for mpll clk source and upll clk source. when om[3:2] = 01b, xtipll is used for mpll clk source only. when om[3:2] = 10b, xtipll is used for upll clk source only. if it isn't used, it has to be a floating pin. notes: 1. i/o means input/output. 2. ai/ao means analog input/output. 3. st means schmitt-trigger. 4. p means power.
s3c2400 risc microprocessor product ov erview 1- 25 table 1-3. s3c2400 signal descriptions (continued) signal i/o description reset & clock & power (continued) mpllcap ai loop filter capacitor for main clock. upllcap ai loop filter capacitor for usb clock. xtirtc ai 32 khz crystal input for rtc. xtortc ao 32 khz crystal output for rtc. clkout o clock output signal. the clksel of misccr register configures the clock output mode among the mpll clk, upll clk, fclk, hclk, pclk. power vddi p s3c2400 core logic vdd(1.8v) for cpu. vssi p s3c2400 core logic vss vddi_mpll p s3c2400 mpll analog and digital vdd (1.8 v). vssi_mpll p s3c2400 mpll analog and digital vss. vddio p s3c2400 i/o port vdd(3.3v) vssio p s3c2400 i/o port vss rtcvdd p rtc vdd ( 1.8 v , not support 3.3v) (this pin must be connected to power properly if rtc isn't used) vddi_upll p s3c2400 upll analog and digital vdd (1.8v) vssi_upll p s3c2400 upll analog and digital vss vdda_adc p s3c2400 adc vdd(3.3v) vssa_adc p s3c2400 adc vss
product overview s3 c2400 risc microprocessor 1- 26 s3c2400 special registers table 1-4. s3c2400 special registers register name address (b. endian) address (l. endian) acc. unit read/ write function memory controller bwscon 0x14000000 ? w r/w bus width & wait status control bankcon0 0x14000004 boot rom control bankcon1 0x14000008 bank1 control bankcon2 0x1400000c bank2 control bankcon3 0x14000010 bank3 control bankcon4 0x14000014 bank4 control bankcon5 0x14000018 bank5 control bankcon6 0x1400001c bank6 control bankcon7 0x14000020 bank7 control refresh 0x14000024 dram/sdram refresh control banksize 0x14000028 flexible bank size mrsrb6 0x1400002c mode register set for sdram mrsrb7 0x14000030 mode register set for sdram
s3c2400 risc microprocessor product ov erview 1- 27 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/ write function usb host controller hcrevision 0x14200000 ? w control and status group hccontrol 0x14200004 hccommonstatus 0x14200008 hcinterruptstatus 0x1420000c hcinterruptenable 0x14200010 hcinterruptdisable 0x14200014 hchcca 0x14200018 memory pointer group hcperiodcuttented 0x1420001c hccontrolheaded 0x14200020 hccontrolcurrented 0x14200024 hcbulkheaded 0x14200028 hcbulkcurrented 0x1420002c hcdonehead 0x14200030 hcrminterval 0x14200034 frame counter group hcfmremaining 0x14200038 hcfmnumber 0x1420003c hcperiodicstart 0x14200040 hclsthreshold 0x14200044 hcrhdescriptora 0x14200048 root hub group hcrhdescriptorb 0x1420004c hcrhstatus 0x14200050 hcrhportstatus1 0x14200054 hcrhportstatus2 0x14200058 interrupt controller srcpnd 0x14400000 ? w r/w interrupt request status intmod 0x14400004 w interrupt mode control intmsk 0x14400008 r/w interrupt mask control priority 0x1440000c w irq priority control intpnd 0x14400010 r/w interrupt request status intoffset 0x14400014 r interrupt request source
product overview s3 c2400 risc microprocessor 1- 28 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/ write function dma disrc0 0x14600000 ? w r/w dma 0 initial source didst0 0x14600004 dma 0 initial destination dcon0 0x14600008 dma 0 control dstat0 0x1460000c r dma 0 count dcsrc0 0x14600010 dma 0 current source address dcdst0 0x14600014 dma 0 current destination address dmasktrig0 0x14600018 r/w dma 0 mask trigger disrc1 0x14600020 ? w r/w dma 1 initial source didst1 0x14600024 dma 1 initial destination dcon1 0x14600028 dma 1 control dstat1 0x1460002c r dma 1 count dcsrc1 0x14600030 dma 1 current source address dcdst1 0x14600034 dma 1 current destination address dmasktrig1 0x14600038 r/w dma 1 mask trigger disrc2 0x14600040 ? w r/w dma 2 initial source didst2 0x14600044 dma 2 initial destination dcon2 0x14600048 dma 2 control dstat2 0x1460004c r dma 2 count dcsrc2 0x14600050 dma 2 current source address dcdst2 0x14600054 dma 2 current destination address dmasktrig2 0x14600058 r/w dma 2 mask trigger disrc3 0x14600060 ? w r/w dma 3 initial source didst3 0x14600064 dma 3 initial destination dcon3 0x14600068 dma 3 control dstat3 0x1460006c r dma 3 count dcsrc3 0x14600060 dma 3 current source address dcdst3 0x14600064 dma 3 current destination address dmasktrig3 0x14600068 r/w dma 3 mask trigger
s3c2400 risc microprocessor product ov erview 1- 29 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/ write function clock & power management locktime 0x14800000 ? w r/w pll lock time counter mpllcon 0x14800004 mpll control upllcon 0x14800008 upll control clkcon 0x1480000c clock generator control clkslow 0x14800010 slow clock control clkdivn 0x14800014 clock divider control lcd controller lcdcon1 0x14a00000 ? w r/w lcd control 1 lcdcon2 0x14a00004 lcd control 2 lcdcon3 0x14a00008 lcd control 3 lcdcon4 0x14a0000c lcd control 4 lcdcon5 0x14a00010 lcd control 5 lcdsaddr1 0x14a00014 stn/tft: frame buffer start address1 lcdsaddr2 0x14a00018 stn/tft: frame buffer start address2 lcdsaddr3 0x14a0001c stn/tft: virtual screen address set redlut 0x14a00020 stn: red lookup table greenlut 0x14a00024 stn: green lookup table bluelut 0x14a00028 stn: blue lookup table dp1_2 0x14a0002c stn: dithering pattern duty 1/2 dp4_7 0x14a00030 stn: dithering pattern duty 4/7 dp3_5 0x14a00034 stn: dithering pattern duty 3/5 dp2_3 0x14a00038 stn: dithering pattern duty 2/3 dp5_7 0x14a0003c stn: dithering pattern duty 5/7 dp3_4 0x14a00040 stn: dithering pattern duty 3/4 dp4_5 0x14a00044 stn: dithering pattern duty 4/5 dp6_7 0x14a00048 stn: dithering pattern duty 6/7 dithmode 0x14a0004c stn: dithering mode tpal 0x14a00050 tft: temporary palette
product overview s3 c2400 risc microprocessor 1- 30 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/ write function uart ulcon0 0x15000000 ? w r/w uart 0 line control ucon0 0x15000004 uart 0 control ufcon0 0x15000008 uart 0 fifo control umcon0 0x1500000c uart 0 modem control utrstat0 0x15000010 r uart 0 tx/rx status uerstat0 0x15000014 uart 0 rx error status ufstat0 0x15000018 uart 0 fifo status umstat0 0x1500001c uart 0 modem status utxh0 0x15000023 0x15000020 b w uart 0 transmission hold urxh0 0x15000027 0x15000024 r uart 0 receive buffer ubrdiv0 0x15000028 ? w r/w uart 0 baud rate divisor ulcon1 0x15004000 ? w r/w uart 1 line control ucon1 0x15004004 uart 1 control ufcon1 0x15004008 uart 1 fifo control umcon1 0x1500400c uart 1 modem control utrstat1 0x15004010 r uart 1 tx/rx status uerstat1 0x15004014 uart 1 rx error status ufstat1 0x15004018 uart 1 fifo status umstat1 0x1500401c uart 1 modem status utxh1 0x15004023 0x15004020 b w uart 1 transmission hold urxh1 0x15004027 0x15004024 r uart 1 receive buffer ubrdiv1 0x15004028 ? w r/w uart 1 baud rate divisor
s3c2400 risc microprocessor product ov erview 1- 31 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/ write function pwm timer tcfg0 0x15100000 ? w r/w timer configuration tcfg1 0x15100004 timer configuration tcon 0x15100008 timer control tcntb0 0x1510000c timer count buffer 0 tcmpb0 0x15100010 timer compare buffer 0 tcnto0 0x15100014 r timer count observation 0 tcntb1 0x15100018 r/w timer count buffer 1 tcmpb1 0x1510001c timer compare buffer 1 tcnto1 0x15100020 r timer count observation 1 tcntb2 0x15100024 r/w timer count buffer 2 tcmpb2 0x15100028 timer compare buffer 2 tcnto2 0x1510002c r timer count observation 2 tcntb3 0x15100030 r/w timer count buffer 3 tcmpb3 0x15100034 timer compare buffer 3 tcnto3 0x15100038 r timer count observation 3 tcntb4 0x1510003c r/w timer count buffer 4 tcnto4 0x15100040 r timer count observation 4
product overview s3 c2400 risc microprocessor 1- 32 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/w rite function usb device func_addr_reg 0x15200140 ? w r/w function address pwr_reg 0x15200144 power management int_reg 0x15200148 r interrupt pending and clear int_mask_reg 0x1520014c r/w interrupt mask frame_num_reg 0x15200150 r frame number resume_con_reg 0x15200154 r/w resume signal control ep0_csr 0x15200160 clock generator control ep0_maxp 0x15200164 end point0 max packet ep0_out_cnt 0x15200168 end point0 out write count ep0_fifo 0x1520016c end point0 fifo read/write ep1_in_csr 0x15200180 end point1 in control status ep1_in_maxp 0x15200184 end point1 in max packet ep1_fifo 0x15200188 w end point2 fifo write ep2_in_csr 0x15200190 r/w end point2 in control status ep2_in_maxp 0x15200194 end point2 in max packet ep2_fifo 0x15200198 w end point2 fifo write ep3_out_csr 0x152001a0 r/w end point3 out control status ep3_out_maxp 0x152001a4 end point3 out max packet ep3_out_cnt 0x152001a8 r end point3 out write count ep3_fifo 0x152001ac end point3 fifo read ep4_out_csr 0x152001b0 r/w end point4 out control status ep4_out_maxp 0x152001b4 end point4 out max packet ep4_out_cnt 0x152001b8 r end point4 out write count ep4_fifo 0x152001bc end point4 fifo read dma_con 0x152001c0 r/w dma interface control dma_unit 0x152001c4 dma transfer unit counter dma_fifo 0x152001c8 dma transfer fifo counter dma_tx 0x152001cc dma total transfer counter test_mode 0x152001f4 w test mode control in_con_reg 0x152001f8 in packet number control
s3c2400 risc microprocessor product ov erview 1- 33 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/ write function watchdog timer wtcon 0x15300000 ? w r/w watch-dog timer mode wtdat 0x15300004 watch-dog timer data wtcnt 0x15300008 watch-dog timer count iic iiccon 0x15400000 ? w r/w iic control iicstat 0x15400004 iic status iicadd 0x15400008 iic address iicds 0x1540000c iic data shift iis iiscon 0x15508000,02 0x15508000 hw,w r/w iis control iismod 0x15508004,06 0x15508004 hw,w iis mode iispsr 0x15508008,0a 0x15508008 hw,w iis prescaler iisfifcon 0x1550800c,0e 0x1550800c hw,w iis fifo control iisfif 0x15508012 0x15508010 hw iis fifo entry
product overview s3 c2400 risc microprocessor 1- 34 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/ write function i/o port pacon 0x15600000 ? w r/w port a control padat 0x15600004 port a data pbcon 0x15600008 port b control pbdat 0x1560000c port b data pbup 0x15600010 pull-up control b pccon 0x15600014 port c control pcdat 0x15600018 port c data pcup 0x1560001c pull-up control c pdcon 0x15600020 port d control pddat 0x15600024 port d data pdup 0x15600028 pull-up control d pecon 0x1560002c port e control pedat 0x15600030 port e data peup 0x15600034 pull-up control e pfcon 0x15600038 port f control pfdat 0x1560003c port f data pfup 0x15600040 pull-up control f pgcon 0x15600044 port g control pgdat 0x15600048 port g data pgup 0x1560004c pull-up control g opencr 0x15600050 open drain enable misccr 0x15600054 miscellaneous control extint 0x15600058 external interrupt control
s3c2400 risc microprocessor product ov erview 1- 35 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/ write function rtc rtccon 0x15700043 0x15700040 b r/w rtc control ticint 0x15700047 0x15700044 tick time count rtcalm 0x15700053 0x15700050 rtc alarm control almsec 0x15700057 0x15700054 alarm second almmin 0x1570005b 0x15700058 alarm minute almhour 0x1570005f 0x1570005c alarm hour almday 0x15700063 0x15700060 alarm day almmon 0x15700067 0x15700064 alarm month almyear 0x1570006b 0x15700068 alarm year rtcrst 0x1570006f 0x1570006c rtc round reset bcdsec 0x15700073 0x15700070 bcd second bcdmin 0x15700077 0x15700074 bcd minute bcdhour 0x1570007b 0x15700078 bcd hour bcdday 0x1570007f 0x1570007c bcd day bcddate 0x15700083 0x15700080 bcd date bcdmon 0x15700087 0x15700084 bcd month bcdyear 0x1570008b 0x15700088 bcd year a/d converter adccon 0x15800000 ? w r/w adc control adcdat 0x15800004 r adc data spi spcon 0x15900000 ? w r/w spi control spsta 0x15900004 r spi status sppin 0x15900008 r/w spi pin control sppre 0x1590000c spi baud rate prescaler sptdat 0x15900010 spi tx data sprdat 0x15900014 r spi rx data
product overview s3 c2400 risc microprocessor 1- 36 table 1-4. s3c2400 special registers (continued) register name address (b. endian) address (l. endian) acc. unit read/ write function mmc interface mmcon 0x15a00000,02,03 0x15a00000 b, hw, w r/w mmc control mmcrr 0x15a00004,06,07 0x15a00004 mmc command mmfcon 0x15a00008,0a,0b 0x15a00008 mmc fifo control mmsta 0x15a0000c,0e,0f 0x15a0000c r mmc status mmfsta 0x15a00010,12 0x15a00010 hw, w mmc fifo status mmpre 0x15a00014,16,17 0x15a00014 b, hw, w r/w mmc baud rate prescaler mmlen 0x15a00018,1a 0x15a00018 hw, w mmc block length mmcr7 0x15a0001c,0e,0f 0x15a0001c b, hw, w r response crc7 mmrsp0 0x15a00020 ? w mmc response status 0 mmrsp1 0x15a00024 mmc response status 1 mmrsp2 0x15a00028 mmc response status 2 mmrsp3 0x15a0002c mmc response status 3 mmcmd0 0x15a00030,32,33 0x15a00030 b, hw, w r/w mmc command 0 mmcmd1 0x15a00034 ? w mmc command 1 mmcr16 0x15a00038,3a 0x15a00038 hw, w r data read crc16 buffer mmdat 0x15a0003c,3e,3f 0x15a0003c b, hw, w r/w mmc data
s3c2400 risc microprocessor product ov erview 1- 37 important notes about s3c2400 special registers 1. in the little endian mode, l. endian address must be used. in the big endian mode, b. endian address must be used. 2. the special registers have to be accessed by the recommended access unit. 3. all registers except adc registers, rtc registers and uart registers must be read/written in word unit (32bit) at little/big endian. 4. it is very important that the adc registers, rtc registers and uart registers be read/written by the specified access unit and the specified address. moreover, one must carefully consider which endian mode is used. 5. w: 32-bit register, which must be accessed by ldr/str or int type pointer( int *). hw: 16-bit register, which must be accessed by ldrh/strh or short int type pointer(short int *). b: 8-bit register, which must be accessed by ldrb/strb or char type pointer(char int *).
S3C2400X01 risc microprocessor programmer 's model 2- 1 2 programmer's model overview S3C2400X01 has been developed using the advanced arm920t core, which has been designed by advanced risc machines, ltd. processor operating states from the programmer's point of view, the arm920t can be in one of two states: arm state which executes 32-bit, word-aligned arm instructions. thumb state which can execute 16-bit, halfword-aligned thumb instructions. in this state, the pc uses bit 1 to select between alternate halfwords. note transition between these two states does not affect the processor mode or the contents of the registers. switching state entering thumb state entry into thumb state can be achieved by executing a bx instruction with the state bit (bit 0) set in the operand register. transition to thumb state will also occur automatically on return from an exception (irq, fiq, undef, abort, swi etc.), if the exception was entered with the processor in thumb state. entering arm state entry into arm state happens: on execution of the bx instruction with the state bit clear in the operand register. on the processor taking an exception (irq, fiq, reset, undef, abort, swi etc.). in this case, the pc is placed in the exception mode's link register, and execution commences at the exception's vector address. memory formats arm920t views memory as a linear collection of bytes numbered upwards from zero. bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. arm920t can treat words in memory as being stored either in big- endian or little-endian format.
programmer's model S3C2400X01 risc mic roprocessor 2- 2 big-endian format in big-endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. byte 0 of the memory system is therefore connected to data lines 31 through 24. 31 8 4 0 23 9 5 1 10 6 2 11 7 3 8 7 0 4 0 8 higher address lower address word address most significant byte is at lowest address. word is addressed by byte address of most significant byte. 24 15 16 figure 2-1. big-endian addresses of bytes within words little-endian format in little-endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the highest numbered byte the most significant. byte 0 of the memory system is therefore connected to data lines 7 through 0. 31 23 8 7 0 4 0 8 higher address lower address word address least significant byte is at lowest address. word is addressed by byte address of least significant byte. 24 15 16 8 4 0 9 5 1 10 6 2 11 7 3 figure 2-2. little-endian addresses of bytes whthin words instruction length instructions are either 32 bits long (in arm state) or 16 bits long (in thumb state). data types arm920t supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. words must be aligned to four-byte boundaries and half words to two-byte boundaries.
S3C2400X01 risc microprocessor programmer 's model 2- 3 operating modes arm920t supports seven modes of operation: user (usr): the normal arm program execution state fiq (fiq): designed to support a data transfer or channel process irq (irq): used for general-purpose interrupt handling supervisor (svc): protected mode for the operating system abort mode (abt): entered after a data or instruction prefetch abort system (sys): a privileged user mode for the operating system undefined (und): entered when an undefined instruction is executed mode changes may be made under software control, or may be brought about by external interrupts or exception processing. most application programs will execute in user mode. the non-user modes' known as privileged modes- are entered in order to service interrupts or exceptions, or to access protected resources. registers arm920t has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. the processor state and operating mode dictate which registers are available to the programmer. the arm state register set in arm state, 16 general registers and one or two status registers are visible at any one time. in privileged (non- user) modes, mode-specific banked registers are switched in. figure 2-3 shows which registers are available in each mode: the banked registers are marked with a shaded triangle. the arm state register set contains 16 directly accessible registers: r0 to r15. all of these except r15 are general- purpose, and may be used to hold either data or address values. in addition to these, there is a seventeenth register used to store status information. register 14 is used as the subroutine link register. this receives a copy of r15 when a branch and link (bl) instruction is executed. at all other times it may be treated as a general- purpose register. the corresponding banked registers r14_svc, r14_irq, r14_fiq, r14_abt and r14_und are similarly used to hold the return values of r15 when interrupts and exceptions arise, or when branch and link instructions are executed within interrupt or exception routines. register 15 holds the program counter (pc). in arm state, bits [1:0] of r15 are zero and bits [31:2] contain the pc. in thumb state, bit [0] is zero and bits [31:1] contain the pc. register 16 is the cpsr (current program status register). this contains condition code flags and the current mode bits. fiq mode has seven banked registers mapped to r8-14 (r8_fiq-r14_fiq). in arm state, many fiq handlers do not need to save any registers. user, irq, supervisor, abort and undefined each have two banked registers mapped to r13 and r14, allowing each of these modes to have a private stack pointer and link registers.
programmer's model S3C2400X01 risc mic roprocessor 2- 4 r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13 r14 r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13_ svc r14_ svc r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r9_ fiq r10_ fiq r11_ fiq r12_ fiq r13_ fiq r14_ fiq r15 (pc) r8_ fiq r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13_ abt r14_ abt r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13_ irq r14_ irq r15 (pc) r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 r13_ und r14_ und r15 (pc) system & user fiq supervisor irq abort undefined arm state general registers and program counter arm state program status registers cpsr cpsr spsr_ fiq cpsr spsr_ irq = banked register cpsr spsr_ und cpsr spsr_ abt cpsr spsr_ svc figure 2-3. register organization in arm state
S3C2400X01 risc microprocessor programmer 's model 2- 5 the thumb state register set the thumb state register set is a subset of the arm state set. the programmer has direct access to eight general registers, r0-r7, as well as the program counter (pc), a stack pointer register (sp), a link register (lr), and the cpsr. there are banked stack pointers, link registers and saved process status registers (spsrs) for each privileged mode. this is shown in figure 2-4. r0 r1 r2 r3 r4 r5 r6 r7 lr sp pc system & user fiq supervisor irq abort undefined thumb state general registers and program counter thumb state program status registers cpsr cpsr spsr_ fiq cpsr spsr_ svc cpsr spsr_ abt cpsr spsr_ irq cpsr spsr_ und = banked register lr_ fiq r0 r1 r2 r3 r4 r5 r6 r7 sp_ fiq pc lr_ svc r0 r1 r2 r3 r4 r5 r6 r7 sp_ svc pc lr_ und r0 r1 r2 r3 r4 r5 r6 r7 sp_ und pc lr_ fiq r0 r1 r2 r3 r4 r5 r6 r7 sp_ fiq pc lr_ abt r0 r1 r2 r3 r4 r5 r6 r7 sp_ ab t pc figure 2-4. register organization in thumb state
programmer's model S3C2400X01 risc mic roprocessor 2- 6 the relationship between arm and thumb state registers the thumb state registers relate to the arm state registers in the following way: thumb state r0-r7 and arm state r0-r7 are identical thumb state cpsr and spsrs and arm state cpsr and spsrs are identical thumb state sp map s onto arm state r13 thumb state lr maps onto arm state r14 the thumb state program counter maps onto the arm state program counter (r15) this relationship is shown in figure 2-5. r0 r1 r2 r3 r4 r5 r6 r7 stack pointer (sp) link register (lr) program counter (pc) cpsr spsr r0 r1 r2 r3 r4 r5 r6 r7 r9 r8 r10 r11 r12 stack pointer (r13) link register (r14) program counter (r15) cpsr spsr lo-registers hi-registers thumb state arm state figure 2-5. mapping of thumb state registers onto arm state registers
S3C2400X01 risc microprocessor programmer 's model 2- 7 accessing hi-registers in thumb state in thumb state, registers r 8-r15 (the hi registers) are not part of the standard register set. however, the assembly language programmer has limited access to them, and can use them for fast temporary storage. a value may be transferred from a register in the range r0-r7 (a lo register) to a hi register, and from a hi register to a lo register, using special variants of the mov instruction. hi register values can also be compared against or added to lo register values with the cmp and add instructions. for more information, refer to figure 3-34. the program status registers the arm920t contains a current program status register (cpsr), plus five saved program status registers (spsrs) for use by exception handlers. these register's functions are: hold information about the most recently p erformed alu operation control the enabling and disabling of interrupts set the processor operating mode the arrangement of bits is shown in figure 2-6. 31 condition code flags overflow n z c v i f t m4 m3 m2 m1 m0 30 29 27 28 26 25 24 23 8 7 6 5 4 3 2 1 0 (reserved) control bits carry/borrow/extend zero negative/less than mode bits state bit fiq disable irq disable ~ ~ ~ ~ figure 2-6. program status register format
programmer's model S3C2400X01 risc mic roprocessor 2- 8 the condition code flags the n, z, c and v bits are the condition code flags. these may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed. in arm state, all instructions may be executed conditionally: see table 3-2 for details. in thumb state, only the branch instruction is capable of conditional execution: see figure 3-46 for details. the control bits the bottom 8 bits of a psr (incorporating i, f, t and m[4:0]) are known collectively as the control bits. these will be changed when an exception arises. if the processor is operating in a privileged mode, they can also be manipulated by software. the t bit this reflects the operating state. when this bit is set, the processor is executing in thumb state, otherwise it is executing in arm state. this is reflected on the tbit external signal. note that the software must never change the state of the tbit in the cpsr. if this happens, the processor will enter an unpredictable state. interrupt disable bits the i and f bits are the interrupt disable bits. when set, these disable the irq and fiq interrupts respectively. the mode bits the m4, m3, m2, m1 and m0 bits (m[4:0]) are the mode bits. these determine the processor's operating mode, as shown in table 2-1. not all combinations of the mode bits define a valid processor mode. only those explicitly described shall be used. the user should be aware that if any illegal value is programmed into the mode bits, m[4:0], then the processor will enter an unrecoverable state. if this occurs, reset should be applied. reserved bits the remaining bits in the psrs are reserved. when changing a psr's flag or control bits, you must ensure that these unused bits are not altered. also, your program should not rely on them containing specific values, since in future processors they may read as one or zero.
S3C2400X01 risc microprocessor programmer 's model 2- 9 table 2-1. psr mode bit values m[4:0] mode visible thumb state registers visible arm state registers 10000 user r7..r0, lr, sp pc, cpsr r14..r0, pc, cpsr 10001 fiq r7..r0, lr_fiq, sp_fiq pc, cpsr, spsr_fiq r7..r0, r14_fiq..r8_fiq, pc, cpsr, spsr_fiq 10010 irq r7..r0, lr_irq, sp_irq pc, cpsr, spsr_irq r12..r0, r14_irq, r13_irq, pc, cpsr, spsr_irq 10011 supervisor r7..r0, lr_svc, sp_svc, pc, cpsr, spsr_svc r12..r0, r14_svc, r13_svc, pc, cpsr, spsr_svc 10111 abort r7..r0, lr_abt, sp_abt, pc, cpsr, spsr_abt r12..r0, r14_abt, r13_abt, pc, cpsr, spsr_abt 11011 undefined r7..r0 lr_und, sp_und, pc, cpsr, spsr_und r12..r0, r14_und, r13_und, pc, cpsr 11111 system r7..r0, lr, sp pc, cpsr r14..r0, pc, cpsr reserved bits the remaining bits in the psr's are reserved. when changing a psr's flag or control bits, you must ensure that these unused bits are not altered. also, your program should not rely on the m containing specific values, since in future processors they may read as one or zero.
programmer's model S3C2400X01 risc mic roprocessor 2- 10 exceptions exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished. it is possible for several exceptions to arise at the same time. if this happens, they are dealt with in a fixed order. see exception priorities on page 2-14. action on entering an exception when handling an exception, the arm920t: 1. preserves the address of the next instruction in the appropriate link register. if the exception has been entered from arm state, then the address of the next instruction is copied into the link register (that is, current pc + 4 or pc + 8 depending on the exception. see table 2-2 on for details). if the exception has been entered from thumb state, then the value written into the link register is the current pc offset by a value such that the program resumes from the correct place on return from the exception. this means that the exception handler need not determine which state the exception was e ntered from. for example, in the case of swi, movs pc, r14_svc will always return to the next instruction regardless of whether the swi was executed in arm or thumb state. 2. copies the cpsr into the appropriate spsr 3. forces the cpsr mode bits to a val ue which depends on the exception 4. forces the pc to fetch the next instruction from the relevant exception vector it may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions. if the processor is in thumb state when an exception occurs, it will automatically switch into arm state when the pc is loaded with the exception vector address. action on leaving an exception on completion, the exception handler: 1. moves the link register, minus an offset where appropriate, to the pc. (the offset will vary depending on the type of exception.) 2. copies the spsr back to the cpsr 3. clears the interrupt disable flags, if they were set on entry note an explicit switch back to thumb state is never needed, since restoring the cpsr from the spsr automatically sets the t bit to the value it held immediately prior to the exception.
S3C2400X01 risc microprocessor programmer 's model 2- 11 exception entry/exit summary table 2-2 summarises the pc value preserved in the relevant r14 on exception entry, and the recommended instruction for exiting the exception handler. table2-2. exception entry/exit return instruction previous state notes arm r14_x thumb r14_x bl mov pc, r14 pc + 4 pc + 2 1 swi movs pc, r14_svc pc + 4 pc + 2 1 udef movs pc, r14_und pc + 4 pc + 2 1 fiq subs pc, r14_fiq, #4 pc + 4 pc + 4 2 irq subs pc, r14_irq, #4 pc + 4 pc + 4 2 pabt subs pc, r14_abt, #4 pc + 4 pc + 4 1 dabt subs pc, r14_abt, #8 pc + 8 pc + 8 3 reset na - - 4 notes: 1. where pc is the address of the bl/swi/undefined instruction fetch which had the prefetch abort. 2. where pc is the address of the instruction which did not get executed since the fiq or irq took priority. 3. where pc is the address of the load or store instruction wh ich generated the data abort. 4. the value saved in r14_svc upon reset is unpredictable. fiq the fiq (fast interrupt request) exception is designed to support a data transfer or channel process, and in arm state has sufficient private registers to remove the need for register saving (thus minimising the overhead of context switching). fiq is externally generated by taking the nfiq input low. this input can except either synchronous or asynchronous transitions, depending on the state of the isync input signal. when isync is low, nfiq and nirq are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow. irrespective of whether the exception was entered from arm or thumb state, a fiq handler should leave the interrupt by executing subs pc,r14_fiq,#4 fiq may be disabled by setting the cpsr's f flag (but note that this is not possible from user mode). if the f flag is clear, arm920t checks for a low level on the output of the fiq synchroniser at the end of each instruction.
programmer's model S3C2400X01 risc mic roprocessor 2- 12 irq the irq (interrupt request) exception is a normal interrupt caused by a low level on the nirq input. irq has a lower priority than fiq and is masked out when a fiq sequence is entered. it may be disabled at any time by setting the i bit in the cpsr, though this can only be done from a privileged (non-user) mode. irrespective of whether the exception was entered from arm or thumb state, an irq handler should return from the interrupt by executing subs pc,r14_irq,#4 abort an abort indicates that the current memory access cannot be completed. it can be signalled by the external abort input. arm920t checks for the abort exception during memory access cycles. there are two types of abort: prefetch abort: occurs during an instruction prefetch. data abort: occurs during a data access. if a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the instruction reaches the head of the pipeline. if the instruction is not executed - for example because a branch occurs while it is in the pipeline - the abort does not take place. if a data abort occurs, the action taken depends on the instruction type: si ngle data transfer instructions (ldr, str) write back modified base registers: the abort handler must be aware of this. the swap instruction (swp) is aborted as though it had not been executed. block data transfer instructions (ldm, stm) complete. if w rite-back is set, the base is updated. if the instruction would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. all register overwriting is prevented after an abort is indicated, which means in particular that r15 (always the last register to be transferred) is preserved in an aborted ldm instruction. the abort mechanism allows the implementation of a demand paged virtual memory system. in such a system the processor is allowed to generate arbitrary addresses. when the data at an address is unavailable, the memory management unit (mmu) signals an abort. the abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. the application program needs no knowledge of the amount of memory available to it, nor is its state in any way affected by the abort. after fixing the reason for the abort, the handler should execute the following irrespective of the state (arm or thumb): subs pc,r14_abt,#4 ; for a prefetch abort, or subs pc,r14_abt,#8 ; for a data abort this restores both the pc and the cpsr, and retries the aborted instruction.
S3C2400X01 risc microprocessor programmer 's model 2- 13 software interrupt the software interrupt instruction (swi) is used for entering supervisor mode, usually to request a particular supervisor function. a swi handler should return by executing the following irrespective of the state (arm or thumb ): mov pc,r14_svc this restores the pc and cpsr, and returns to the instruction following the swi. note nfiq, nirq, isync, lock, bigend, and abort pins exist only in the arm920t cpu core. undefined instruction when arm920t comes across an instruction which it cannot handle, it takes the undefined instruction trap. this mechanism may be used to extend either the thumb or arm instruction set by software emulation. after emulating the failed instruction, the trap handler should execute the following irrespective of the state (arm or thumb): movs pc,r14_u nd this restores the cpsr and returns to the instruction following the undefined instruction. exception vectors the following table shows the exception vector addresses. table 2-3. exception vectors address exception mode in entry 0x00000000 reset supervisor 0x00000004 undefined instruction undefined 0x00000008 software interrupt supervisor 0x0000000c abort (prefetch) abort 0x00000010 abort (data) abort 0x00000014 reserved reserved 0x00000018 irq irq 0x0000001c fiq fiq
programmer's model S3C2400X01 risc mic roprocessor 2- 14 exception priorites when multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: highest priority: 1. reset 2. data abort 3. fiq 4. irq 5. prefetch abort lowest priority: 6. undefined instruction, software interrupt. not all exceptions can occur at once: undefined instruction and software interrupt are mutually exclusive, since they each correspond to particular (non- overlapping) decodings of the current instruction. if a data abort occurs at the same time as a fiq, and fiqs are enabled (ie the cpsr's f flag is clear), arm920t enters the data abort handler and then immediately proceeds to the fiq vector. a normal return from fiq will cause the data abort handler to resume execution. placing data abort at a higher priority than fiq is necessary to ensure that the transfer error does not escape detection. the time for this exception entry should be added to worst-case fiq latency calculations .
S3C2400X01 risc microprocessor programmer 's model 2- 15 interrupt latencies the worst case latency for fiq, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser ( tsyncmax if asynchronous), plus the time for the longest instruction to complete ( tldm , the longest instruction is an ldm which loads all the registers including the pc), plus the time for the data abort entry ( texc ), plus the time for fiq entry ( tfiq ). at the end of this time arm920t will be executing the instruction at 0x1c. tsyncmax is 3 processor cycles, tldm is 20 cycles, texc is 3 cycles, and tfiq is 2 cycles. the total time is therefore 28 processor cycles. this is just over 1.4 microseconds in a system which uses a continuous 20 mhz processor clock. the maximum irq latency calculation is similar, but must allow for the fact that fiq has higher priority and could delay entry into the irq handling routine for an arbitrary length of time. the minimum latency for fiq or irq consists of the shortest time the request can take through the synchroniser ( tsyncmin ) plus tfiq . this is 4 processor cycles. reset when the nreset signal goes low, arm920t abandons the executing instruction and then continues to fetch instructions from incrementing word addresses. when nreset goes high again, arm920t: 1. overwrites r14_svc and spsr_svc by copying the current values of the pc and cpsr into them. the value of the saved pc and spsr is not defined. 2. forces m[4:0] to 10011 (supervisor mode), sets the i and f bits in the cpsr, and clears the cpsr's t bit. 3. forces the pc to fetch the next instruction from address 0x00. 4. execution resumes in arm state.
programmer's model S3C2400X01 risc mic roprocessor 2- 16 notes
s3c2400 risc microprocessor arm instruction set 3- 1 3 arm instruction set instruction set summay this chapter describes the arm instruction set in the arm920t core. format summary the arm instruction set formats are shown below. cond rn data/processing/ psr transfer 0 0 i s opcode 0 0 0 p u 0 w l 0 0 0 p u 1 w l 0 1 i p u b w l 0 1 i 1 0 0 p u b w l 1 1 1 1 1 1 1 1 1 0 l 1 1 1 0 p u b w l 1 1 1 1 1 1 0 1 1 1 0 1 l rd rd rn rdhi rdlo rn rn rn rn rd rd rd rn register list rn crn crn crd rd cp opc cp opc operand2 rs rm rm rm rm rn rn rd offset offset crd offset cp# cp# cp# cp cp crm crm ignored by processor 0 1 offset cond cond cond cond cond cond cond cond cond cond cond cond cond cond 0 0 0 0 0 0 a s a s u 1 0 0 0 0 0 0 0 0 0 0 1 b 1 0 0 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 h h 0 0 0 0 s s 1 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 multiply multiply long single data swap branch and exchange halfword data transfer: register offset halfword data transfer: immendiate offset single data transfer undefined block data transfer branch coprocessor register transfer coprocessor data operation coprocessor data transfer software interrupt offset 27 26 25 24 23 22 21 20 19 18 17 16 15 13 14 12 11 10 31 30 29 28 9 8 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 19 18 17 16 15 13 14 12 11 10 31 30 29 28 9 8 7 6 5 4 3 2 1 0 figure 3-1. arm instruction set format
arm instruction set s3c2400 risc micro processor 3- 2 notes some instruction codes are not defined but do not cause the undefined instruction trap to be taken, for instance a multiply instruction with bit 6 changed to a 1. these instructions should not be used, as their action may change in future arm implementations. instruction summary table 3-1. the arm instruction set mnemonic instruction action adc add with carry rd: = rn + op2 + carry add add rd: = rn + op2 and and rd: = rn and op2 b branch r15: = address bic bit clear rd: = rn and not op2 bl branch with link r14: = r15, r15: = address bx branch and exchange r15: = rn, t bit: = rn[0] cdp coprocessor data processing (coprocessor-specific) cmn compare negative cpsr flags: = rn + op2 cmp compare cpsr flags: = rn - op2 eor exclusive or rd: = ( rn and not op2) or (op2 and not rn) ldc load coprocessor from memory coprocessor load ldm load multiple registers stack manipulation (pop) ldr load register from memory rd: = (address) mcr move cpu register to coprocessor register crn: = rrn {crm} mla multiply accumulate rd: = ( rm rs) + rn mov move register or constant rd: = op2
s3c2400 risc microprocessor arm instruction set 3- 3 table 3-1. the arm instruction set (continued) mnemonic instruction action mrc move from coprocessor register to cpu register rn: = crn {crm} mrs move psr status/flags to register rn: = psr msr move register to psr status/flags psr: = rm mul multiply rd: = rm rs mvn move negative register rd: = 0 ffffffff eor op2 orr or rd: = rn or op2 rsb reverse subtract rd: = op2 - rn rsc reverse subtract with carry rd: = op2 - rn - 1 + carry sbc subtract with carry rd: = rn - op2 - 1 + carry stc store coprocessor register to memory address: = crn stm store multiple stack manipulation (push) str store register to memory

: = rd sub subtract rd: = rn - op2 swi software interrupt os call swp swap register with memory rd: = [ rn], [ rn] := rm teq test bitwise equality cpsr flags: = rn eor op2 tst test bits cpsr flags: = rn and op2
arm instruction set s3c2400 risc micro processor 3- 4 the condition field in arm state, all instructions are conditionally executed according to the state of the cpsr condition codes and the instruction's condition field. this field (bits 31:28) determines the circumstances under which an instruction is to be executed. if the state of the c, n, z and v flags fulfils the conditions encoded by the field, the instruction is executed, otherwise it is ignored. there are sixteen possible conditions, each represented by a two-character suffix that can be appended to the instruction's mnemonic. for example, a branch (b in assembly language) becomes beq for "branch if equal", which means the branch will only be taken if the z flag is set. in practice, fifteen different conditions may be used: these are listed in table 3-2. the sixteenth (1111) is reserved, and must not be used. in the absence of a suffix, the condition field of most instructions is set to "always" (suffix al). this means the instruction will always be executed regardless of the cpsr condition codes. table 3-2. condition code summary code suffix flags meaning 0000 eq z set equal 0001 ne z clear not equal 0010 cs c set unsigned higher or same 0011 cc c clear unsigned lower 0100 mi n set negative 0101 pl n clear positive or zero 0110 vs v set overflow 0111 vc v clear no overflow 1000 hi c set and z clear unsigned higher 1001 ls c clear or z set unsigned lower or same 1010 ge n equals v greater or equal 1011 lt n not equal to v less than 1100 gt z clear and (n equals v) greater than 1101 le z set or (n not equal to v) less than or equal 1110 al (ignored) always
s3c2400 risc microprocessor arm instruction set 3- 5 branch and exchange (bx) this instruction is only executed if the condition is true. the various conditions are defined in table 3-2. this instruction performs a branch by copying the contents of a general register, rn, into the program counter, pc. the branch causes a pipeline flush and refill from the address specified by rn. this instruction also permits the instruction set to be exchanged. when the instruction is executed, the value of rn[0] determines whether the instruction stream will be decoded as arm or thumb instructions. 31 24 27 19 15 8 7 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 cond rn 28 16 11 12 23 20 4 3 [3:0] operand register if bit0 of rn = 1, subsequent instructions decoded as thumb instructions if bit0 of rn =0, subsequent instructions decoded as arm instructions [31:28] condition field figure 3-2. branch and exchange instructions instruction cycle times the bx instruction takes 2s + 1n cycles to execute, where s and n are defined as sequential (s-cycle) and non- sequential (n-cycle), respectively. assembler syntax bx - branch and exchange. bx { cond} rn { cond} two character condition mnemonic. see table 3-2. rn is an expression evaluating to a valid register number. using r15 as an operand if r15 is used as an operand, the behavior is undefined.
arm instruction set s3c2400 risc micro processor 3- 6 examples adr r0, into_thumb + 1 ; generate branch target address ; and set bit 0 high - hence ; arrive in thumb state. bx r0 ; branch and change to thumb ; state. code16 ; assemble subsequent code as into_thumb ; thumb instructions adr r5, back_to_arm ; generate branch target to word aligned address ; - hence bit 0 is low and so change back to arm state. bx r5 ; branch and change back to arm state. align ; word align code32 ; assemble subsequent code as arm instructions back_to_arm
s3c2400 risc microprocessor arm instruction set 3- 7 branch and branch with link (b, bl) the instruction is only executed if the condition is true. the various conditions are defined table 3-2. the instruction encoding is shown in figure 3-3, below. 31 24 27 cond offset 28 23 [24] link bit 0 = branch 1 = branch with link [31:28] condition field 25 101 l 0 figure 3-3. branch instructions branch instructions contain a signed 2's complement 24 bit offset. this is shifted left two bits, sign extended to 32 bits, and added to the pc. the instruction can therefore specify a branch of +/- 32mbytes. the branch offset must take account of the prefetch operation, which causes the pc to be 2 words (8 bytes) ahead of the current instruction. branches beyond +/- 32mbytes must use an offset or absolute destination which has been previously loaded into a register. in this case the pc should be manually saved in r14 if a branch with link type operation is required. the link bit branch with link (bl) writes the old pc into the link register (r14) of the current bank. the pc value written into r14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. note that the cpsr is not saved with the pc and r14[1:0] are always cleared. to return from a routine called by branch with link use mov pc,r14 if the link register is still valid or ldm rn!,{..pc} if the link register has been saved onto a stack pointed to by rn. instruction cycle times branch and branch with link instructions take 2s + 1n incremental cycles, where s and n are defined as sequential (s-cycle) and internal (i-cycle).
arm instruction set s3c2400 risc micro processor 3- 8 assembler syntax items in {} are optional. items in <> must be present. b{l}{ cond} {l} used to request the branch with link form of the instruction. if absent, r14 will not be affected by the instruction. { cond} a two-character mnemonic as shown in table 3-2. if absent then al ( always) will be used. the destination. the assembler calculates the offset. examples here bal here ; assembles to 0xeafffffe (note effect of pc offset). b there ; alw ays condition used as default. cmp r1,#0 ; compare r1 with zero and branch to fred ; if r1 was zero, otherwise continue. beq fred ; continue to next instruction. bl sub+rom ; call subroutine at computed address. adds r1,#1 ; add 1 to register 1 , setting cpsr flags ; on the result then call subroutine if blcc sub ; the c flag is clear, which will be the ; case unless r1 held 0xffffffff.
s3c2400 risc microprocessor arm instruction set 3- 9 data processing the data processing instruction is only executed if the condition is true. the conditions are defined in table 3-2. the instruction encoding is shown in figure 3-4. 31 24 27 19 15 cond operand2 28 16 11 12 21 [15:12] destination register 0 = branch 1 = branch with link [19:16] 1st operand register 0 = branch 1 = branch with link [20] set condition codes 0 = do not after condition codes 1 = set condition codes [24:21] operation codes 0000 = and-rd: = op1 and op2 0001 = eor-rd: = op1 eor op2 0010 = sub-rd: = op1-op2 0011 = rsb-rd: = op2-op1 0100 = add-rd: = op1+op2 0101 = adc-rd: = op1+op2+c 0110 = sbc-rd: = op1-op2+c-1 0111 = rsc-rd: = op2-op1+c-1 1000 = tst-set condition codes on op1 and op2 1001 = teo-set condition codes on op1 eor op2 1010 = cmp-set condition codes on op1-op2 1011 = smn-set condition codes on op1+op2 1100 = orr-rd: = op1 or op2 1101 = mov-rd: =op2 1110 = bic-rd: = op1 and not op2 1111 = mvn-rd: = not op2 [25] immediate operand 0 = operand 2 is a register 1 = operand 2 is an immediate value [11:0] operand 2 type selection 26 25 00 l 20 opcode s rn rd 0 rotate shift rm [3:0] 2nd operand register [11:4] shift applied to rm 3 11 0 4 8 11 0 7 imm [7:0] unsigned 8 bit immediate value [11:8] shift applied to imm [31:28] condition field figure 3-4. data processing instructions
arm instruction set s3c2400 risc micro processor 3- 10 the instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. the first operand is always a register ( rn). the second operand may be a shifted register ( rm) or a rotated 8 bit immediate value ( imm) according to the value of the i bit in the instruction. the condition codes in the cpsr may be preserved or updated as a result of this instruction, according to the value of the s bit in the instruction. certain operations (tst, teq, cmp, cmn) do not write the result to rd. they are used only to perform tests and to set the condition codes on the result and always have the s bit set. the instructions and their effects are listed in table 3-3.
s3c2400 risc microprocessor arm instruction set 3- 11 cpsr flags the data processing operations may be classified as logical or arithmetic. the logical operations (and, eor, tst, teq, orr, mov, bic, mvn) perform the logical action on all corresponding bits of the operand or operands to produce the result. if the s bit is set (and rd is not r15, see below) the v flag in the cpsr will be unaffected, the c flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is lsl #0), the z flag will be set if and only if the result is all zeros, and the n flag will be set to the logical value of bit 31 of the result. table 3-3. arm data processing instructions assembler mnemonic op code action and 0000 operand1 and operand2 eor 0001 operand1 eor operand2 wub 0010 operand1 - operand2 rsb 0011 operand2 operand1 add 0100 operand1 + operand2 adc 0101 operand1 + operand2 + carry sbc 0110 operand1 - operand2 + carry - 1 rsc 0111 operand2 - operand1 + carry - 1 tst 1000 as and, but result is not written teq 1001 as eor, but result is not written cmp 1010 as sub, but result is not written cmn 1011 as add, but result is not written orr 1100 operand1 or operand2 mov 1101 operand2 (operand1 is ignored) bic 1110 operand1 and not operand2 (bit clear) mvn 1111 not operand2 (operand1 is ignored) the arithmetic operations (sub, rsb, add, adc, sbc, rsc, cmp, cmn) treat each operand as a 32 bit integer (either unsigned or 2's complement signed, the two are equivalent). if the s bit is set (and rd is not r15) the v flag in the cpsr will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were considered unsigned, but warns of a possible error if the operands were 2's complement signed. the c flag will be set to the carry out of bit 31 of the alu, the z flag will be set if and only if the result was zero, and the n flag will be set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's complement signed).
arm instruction set s3c2400 risc micro processor 3- 12 shifts when the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the shift field in the instruction. this field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). the amount by which the register should be shifted may be contained in an immediate field in the instruction, or in the bottom byte of another register (other than r15). the encoding for the different shift types is shown in figure 3-5. 0 [6:5] shift type 00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right [11:7] shift amount 5 bit unsigned integer [6:5] shift type 00 = logical left 01 = logical right 10 = arithmetic right 11 = rotate right [11:8] shift register shift amount specified in bottom-byte of rs 4 5 6 7 11 1 4 5 6 7 11 8 0 rs figure 3-5. arm shift operations instruction specified shift amount when the shift amount is specified in the instruction, it is contained in a 5 bit field which may take any value from 0 to 31. a logical shift left (lsl) takes the contents of rm and moves each bit by the specified amount to a more significant position. the least significant bits of the result are filled with zeros, and the high bits of rm which do not map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output which may be latched into the c bit of the cpsr when the alu operation is in the logical class (see above). for example, the effect of lsl?#5 is shown in figure 3-6. 31 27 26 contents of rm value of operand 2 carry out 0 0 0 0 0 0 figure 3-6. logical shift left notes lsl #0 is a special case, where the shifter carry out is the old value of the cpsr c flag. the contents of rm are used directly as the second operand. a logical shift right (lsr) is similar, but the contents of rm are moved to less significant positions in the result. lsr #5 has the effect shown in figure 3-7 .
s3c2400 risc microprocessor arm instruction set 3- 13 31 contents of rm value of operand 2 0 carry out 4 5 0 0 0 0 0 figure 3-7. logical shift right the form of the shift field which might be expected to correspond to lsr #0 is used to encode lsr #32, which has a zero result with bit 31 of rm as the carry output. logical shift right zero is redundant as it is the same as logical shift left zero, so the assembler will convert lsr #0 (and asr #0 and ror #0) into lsl #0, and allow lsr #32 to be specified. an arithmetic shift right (asr) is similar to logical shift right, except that the high bits are filled with bit 31 of rm instead of zeros. this preserves the sign in 2's complement notation. for example, asr #5 is shown in figure 3-8. 31 contents of rm value of operand 2 0 carry out 4 5 30 figure 3-8. arithmetic shift right the form of the shift field which might be expected to give asr #0 is used to encode asr #32. bit 31 of rm is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of rm. the result is therefore all ones or all zeros, according to the value of bit 31 of rm.
arm instruction set s3c2400 risc micro processor 3- 14 rotate right (ror) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations. for example, ror #5 is shown in figure 3-9. 31 contents of rm value of operand 2 0 carry out 4 5 figure 3-9. rotate right the form of the shift field which might be expected to give ror #0 is used to encode a special function of the barrel shifter, rotate right extended ( rrx). this is a rotate right by one bit position of the 33 bit quantity formed by appending the cpsr c flag to the most significant end of the contents of rm as shown in figure 3-10. 31 contents of rm value of operand 2 0 1 carry out c in figure 3-10. rotate right extended
s3c2400 risc microprocessor arm instruction set 3- 15 register specified shift amount only the least significant byte of the contents of rs is used to determine the shift amount. rs can be any general register other than r15. if this byte is zero, the unchanged contents of rm will be used as the second operand, and the old value of the cpsr c flag will be passed on as the shifter carry output. if the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation. if the value in the byte is 32 or more, the result will be a logical extension of the shift described above: 1. lsl by 32 has result zero, carry out equal to bit 0 of rm. 2. lsl by more than 32 has result zero, carry out zero. 3. lsr by 32 has result zero, carry out e qual to bit 31 of rm. 4. lsr by more than 32 has result zero, carry out zero. 5. asr by 32 or more has result filled with and carry out equal to bit 31 of rm. 6. ror by 32 has result equal to rm, carry out equal to bit 31 of rm. 7. ror by n where n is greater than 32 will give the same result and carry out as ror by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above. notes the zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction.
arm instruction set s3c2400 risc micro processor 3- 16 immediate operand rotates the immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value. this value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field. this enables many common constants to be generated, for example all powers of 2. writing to r15 when rd is a register other than r15, the condition code flags in the cpsr may be updated from the alu flags as described above. when rd is r15 and the s flag in the instruction is not set the result of the operation is placed in r15 and the cpsr is unaffected. when rd is r15 and the s flag is set the result of the operation is placed in r15 and the spsr corresponding to the current mode is moved to the cpsr. this allows state changes which atomically restore both pc and cpsr. this form of instruction should not be used in user mode. using r15 as an operandy if r15 (the pc) is used as an operand in a data processing instruction the register is used directly. the pc value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. if the shift amount is specified in the instruction, the pc will be 8 bytes ahead. if a register is used to specify the shift amount the pc will be 12 bytes ahead. teq, tst, cmp and cmn opcodes notes teq, tst, cmp and cmn do not write the result of their operation but do set flags in the cpsr. an assembler should always set the s flag for these instructions even if this is not specified in the mnemonic. the teqp form of the teq instruction used in earlier arm processors must not be used: the psr transfer operations should be used instead. the action of teqp in the arm920t is to move spsr_ to the cpsr if the processor is in a privileged mode and to do nothing if in user mode. instruction cycle times data processing instructions vary in the number of incremental cycles taken as follows: table 3-4. incremental cycle times processing type cycles normal data processing 1s data processing with register specified shift 1s + 1i data processing with pc written 2s + 1n data processing with register specified shift and pc written 2s + 1n +1i note: s, n and i are as defined sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle) respectively.
s3c2400 risc microprocessor arm instruction set 3- 17 assembler syntax mov,mvn (single operand instructions). < opcode>{ cond}{s} rd, cmp,cmn,teq,tst (instructions which do not produce a result). < opcode>{ cond} rn, and,eor,sub,r sb,add,adc,sbc,rsc,orr,bic < opcode>{ cond}{s} rd,rn, where: rm{,} or,<#expression> { cond} a two-character condition mnemonic. see table 3-2. {s} set condition codes if s present (implied for cmp, cmn, teq, tst). rd, rn and rm expr essions evaluating to a register number. <#expression> if this is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. if this is impossible, it will give an error. < shiftname> or < shiftname> #expression, or rrx (rotate right one bit with extend). < shiftname>s asl, lsl, lsr, asr, ror. (asl is a synonym for lsl, they assemble to the same code.) examples addeq r2,r4,r5 ; if the z flag is set make r2:=r4+r5 teqs r4,#3 ; t est r4 for equality with 3. ; (the s is in fact redundant as the ; assembler inserts it automatically.) sub r4,r5,r7,lsr r2 ; logical right shift r7 by the number in ; the bottom byte of r2, subtract result ; from r5, and put the answer i nto r4. mov pc,r14 ; return from subroutine. movs pc,r14 ; return from exception and restore cpsr ; from spsr_mode.
arm instruction set s3c2400 risc micro processor 3- 18 psr transfer (mrs, msr) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the mrs and msr instructions are formed from a subset of the data processing operations and are implemented using the teq, tst, cmn and cmp instructions without the s flag set. the encoding is shown in figure 3-11. these instructions allow access to the cpsr and spsr registers. the mrs instruction allows the contents of the cpsr or spsr_ to be moved to a general register. the msr instruction allows the contents of a general register to be moved to the cpsr or spsr_ register. the msr instruction also allows an immediate value or register contents to be transferred to the condition code flags (n,z,c and v) of cpsr or spsr_ without affecting the control bits. in this case, the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant psr. operand restrictions in user mode, the control bits of the cpsr are protected from change, so only the condition code flags of the cpsr can be changed. in other (privileged) modes the entire cpsr can be changed. note that the software must never change the state of the t bit in the cpsr. if this happens, the processor will enter an unpredictable state. the spsr register which is accessed depends on the mode at the time of execution. for example, only spsr_fiq is accessible when the processor is in fiq mode. you must not specify r15 as the source or destination registe r. also, do not attempt to access an spsr in user mode, since no such register exists.
s3c2400 risc microprocessor arm instruction set 3- 19 msr (transfer register contents or immediate value to psr flag bits only) cond source operand pd 101001111 31 22 27 28 11 12 21 23 i 10 00 26 25 24 0 cond 00000000 00010 pd 101001111 31 22 27 28 11 12 21 23 rm msr (transfer register contents to psr) 4 3 0 cond 000000000000 00010 rd ps 001111 31 22 27 15 28 16 11 12 21 23 mrs (transfer psr contents to a register) 0 [3:0] source register [22] destination psr 0 = cpsr 1 = spsr_ [31:28] condition field [15:12] destination register [22] source psr 0 = cpsr 1 = spsr_ [31:28] condition field [3:0] source register [11:4] source operand is an immediate value [7:0] unsigned 8 bit immediate value [11:8] shift applied to imm [22] destination psr 0 = cpsr 1 = spsr_ [25] immediate operand 0 = source operand is a register 1 = spsr_ [11:0] source operand [31:28] condition field 00000000 rm 11 4 3 0 rotate imm 11 0 8 7 figure 3-11. psr transfer
arm instruction set s3c2400 risc micro processor 3- 20 reserved bits only twelve bits of the psr are defined in arm920t (n,z,c,v,i,f, t & m[4:0]); the remaining bits are reserved for use in future versions of the processor. refer to figure 2-6 for a full description of the psr bits. to ensure the maximum compatibility between arm920t programs and future processors, the following rules should be observed: the reserved bits should be preserved when changing the value in a psr. programs should not rely on specific values from the reserved bits when checking the psr status, since they may read as one or zero in future processors. a read-modify-write strategy should therefore be used when altering the control bits of any psr register; this involves transferring the appropriate psr register to a general register using the mrs instruction, changing only the relevant bits and then transferring the modified value back to the psr register using the msr instruction. examples the following sequence performs a mode change: mrs r0,cpsr ; take a copy of the cpsr. bic r0,r0,#0x1f ; clear the mode bits. orr r0,r0,#new_mode ; select new mode msr cpsr,r 0 ; write back the modified cpsr. when the aim is simply to change the condition code flags in a psr, a value can be written directly to the flag bits without disturbing the control bits. the following instruction sets the n,z,c and v flags: msr cpsr_flg, #0xf0000000 ; set all the flags regardless of their previous state ; (does not affect any control bits). no attempt should be made to write an 8 bit immediate value into the whole psr since such an operation cannot preserve the reserved bits. instruction cycle times psr transfers take 1s incremental cycles, where s is defined as sequential (s-cycle).
s3c2400 risc microprocessor arm instruction set 3- 21 assembly syntax mrs - transfer psr contents to a register mrs{ cond} rd, msr - tra nsfer register contents to psr msr{ cond} < psr>, rm msr - transfer register contents to psr flag bits only msr{ cond} < psrf>, rm the most significant four bits of the register contents are written to the n,z,c & v flags respectively. msr - transfer immediate value to psr flag bits only msr{ cond} < psrf>,<#expression> the expression should symbolise a 32 bit value of which the most significant four bits are written to the n,z,c and v flags respectively. key: { cond} two-character condition mnemonic. see table 3-2.. rd and rm expressions evaluating to a register number other than r15 < psr> cpsr, cpsr_all, spsr or spsr_all. (cpsr and cpsr_all are synonyms as are spsr and spsr_all) < psrf> cpsr_flg or spsr_flg <#expression> where this is used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. if this is impossible, it will give an error. examples in user mode the instructions behave as follows: msr cpsr_all,rm ; cpsr[31:28] <- rm[31:28] msr cpsr_flg,rm ; cpsr[31:28] <- rm[31:28] msr cpsr_flg,#0xa0000000 ; cpsr[31:28] <- 0xa (set n,c; clear z,v) mrs rd,cpsr ; rd[31:0] <- cpsr[31:0] in privileged modes the instructions behave as follows: msr cpsr_all,rm ; cpsr[31:0] <- rm[31:0] msr cpsr_flg,rm ; cpsr[31:28] <- rm[31:28] msr cpsr_flg,#0x50000000 ; cpsr[31:28] <- 0x5 (set z,v; clear n,c) msr spsr_all,rm ; spsr_[31:0]<- rm[31:0] msr spsr_flg,rm ; spsr_[31:28] <- rm[31:28] msr spsr_flg,#0xc0000000 ; spsr_[31:28] <- 0xc (set n,z; clear c,v) mrs rd,spsr ; rd[31:0] <- spsr_[31:0]
arm instruction set s3c2400 risc micro processor 3- 22 multiply and multiply-accumulate (mul, mla) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-12. the multiply and multiply-accumulate instructions use an 8 bit booth's algorithm to perform integer multiplication. 31 27 19 15 cond 28 16 11 12 21 20 s rd rn [15:12][11:8][3:0] operand registers [19:16] destination register [20] set condition code 0 = do not after condition codes 1 = set condition codes [21] accumulate 0 = multiply only 1 = multiply and accumulate [31:28] condition field 22 1 0 0 1 rs rm a 0 0 0 0 0 0 8 7 4 3 0 figure 3-12. multiply instructions the multiply form of the instruction gives rd:=rm*rs. rn is ignored, and should be set to zero for compatibility with possible future upgrades to the instruction set. the multiply-accumulate form gives rd:=rm*rs+rn, which can save an explicit add instruction in some circumstances. both forms of the instruction work on operands which may be considered as signed (2's complement) or unsigned integers. the results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits - the low 32 bits of the signed and unsigned results are identical. as these instructions only produce the low 32 bits of a multiply, they can be used for both signed and unsigned multiplies. for example consider the multiplication of the operands: operand a operand b result 0xfffffff6 0x0000001 0xffffff38
s3c2400 risc microprocessor arm instruction set 3- 23 if the operands are interpreted as signed operand a has the value -10, operand b has the value 20, and the result is -200 which is correctly represented as 0xffffff38. if the operands are interpreted as unsigned operand a has the value 4294967286, operand b has the value 20 and the result is 85899345720, which is represented as 0x13ffffff38, so the least significant 32 bits are 0xffffff38. operand restrictions the destination register rd must not be the same as the operand register rm. r15 must not be used as an operand or as the destination register. all other register combinations will give correct results, and rd, rn and rs may use the same register when required.
arm instruction set s3c2400 risc micro processor 3- 24 cpsr flags setting the cpsr flags is optional, and is controlled by the s bit in the instruction. the n (negative) and z (zero) flags are set correctly on the result (n is made equal to bit 31 of the result, and z is set if and only if the result is zero). the c (carry) flag is set to a meaningless value and the v ( overflow) flag is unaffected. instruction cycle times mul takes 1s + mi and mla 1s + (m+1)i cycles to execute, where s and i are defined as sequential (s-cycle) and internal (i-cycle), respectively. m the number of 8 bit mult iplier array cycles is required to complete the multiply, which is controlled by the value of the multiplier operand specified by rs. its possible values are as follows 1 if bits [32:8] of the multiplier operand are all zero or all one. 2 if bits [32:16] of the multiplier operand are all zero or all one. 3 if bits [32:24] of the multiplier operand are all zero or all one. 4 in all other cases. assembler syntax mul{ cond}{s} rd,rm,rs mla{ cond}{s} rd,rm,rs,rn { cond} two-character con dition mnemonic. see table 3-2.. {s} set condition codes if s present rd, rm, rs and rn expressions evaluating to a register number other than r15. examples mul r1,r2,r3 ; r1:=r2*r3 mlaeqs r1,r2,r3,r4 ; conditionally r1:=r2*r3+r4, setting condition codes.
s3c2400 risc microprocessor arm instruction set 3- 25 multiply long and multiply-accumulate long (mull, mlal) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-13. the multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results. signed and unsigned multiplication each with optional accumulate give rise to four variations. 31 27 19 15 cond 28 16 11 12 21 23 u 20 s rdhi rdlo [11:8][3:0] operand registers [19:16][15:12] source destination registers [20] set condition code 0 = do not alter condition codes 1 = set condition codes [21] accumulate 0 = multiply only 1 = multiply and accumulate [22] unsigned 0 = unsigned 1 = signed [31:28] condition field 22 0 0 0 0 1 1 0 0 1 rs rm a 8 7 4 3 0 figure 3-13. multiply long instructions the multiply forms (umull and smull) take two 32 bit numbers and multiply them to produce a 64 bit result of the form rdhi,rdlo := rm * rs. the lower 32 bits of the 64 bit result are written to rdlo, the upper 32 bits of the result are written to rdhi. the multiply-accumulate forms (umlal and smlal) take two 32 bit numbers, multiply them and add a 64 bit number to produce a 64 bit result of the form rdhi,rdlo := rm * rs + rdhi,rdlo. the lower 32 bits of the 64 bit number to add is read from rdlo. the upper 32 bits of the 64 bit number to add is read from rdhi. the lower 32 bits of the 64 bit result are written to rdlo. the upper 32 bits of the 64 bit result are written to rdhi. the umull and umlal instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result. the smull and smlal instructions treat all of their operands as two's-complement signed numbers and write a two's-complement signed 64 bit result.
arm instruction set s3c2400 risc micro processor 3- 26 operand restrictions r15 must not be used as an operand or as a destination register. rdhi, rdlo, and rm must all specify different registers. cpsr flags setting the cpsr flags is optional, and is controlled by the s bit in the instruction. the n and z flags are set correctly on the result (n is equal to bit 63 of the result, z is set if and only if all 64 bits of the result are zero). both the c and v flags are set to meaningless values. instruction cycle times mull takes 1s + (m+1)i and mlal 1s + (m+2)i cycles to execute, where m is the number of 8 bit multiplier array cycles required to complete the multiply, which is controlled by the value of the multiplier operand specified by rs. its possible values are as follows: for signed instructions smull, smlal: if bits [31:8] of the multiplier operand are all zero or all one. if bits [31:16] of the multiplier operand are all zero or all one. if bits [31:24] of the multiplier operand are all zero or all one. in all other cases. for unsigned instructions umull, umlal: if bits [31:8] of the multiplier operand are all zero. if bits [31:16] of the multiplier operand are all zero. if bits [31:24] of the multiplier operand are all zero. in all other cases. s and i are defined as sequential (s-cycle) and internal (i-cycle), respectively.
s3c2400 risc microprocessor arm instruction set 3- 27 assembler syntax table 3-5. assembler syntax descriptions mnemonic description purpose umull{ cond}{s} rdlo,rdhi,rm,rs unsigned multiply long 32 x 32 = 64 umlal{ cond}{s} rdlo,rdhi,rm,rs unsigned multiply & accumulate long 32 x 32 + 64 = 64 smull{ cond}{s} rdlo,rdhi,rm,rs signed multiply long 32 x 32 = 64 smlal{ cond}{s} rdlo,rdhi,rm,rs signed multiply & accumulate long 32 x 32 + 64 = 64 where: { cond} two-character condition mnemonic. see table 3-2. {s} set condition codes if s present rdlo, rdhi, rm, rs expressions evaluating to a register number ot her than r15. examples umull r1,r4,r2,r3 ; r4,r1:=r2*r3 umlals r1,r5,r2,r3 ; r5,r1:=r2*r3+r5,r1 also setting condition codes
arm instruction set s3c2400 risc micro processor 3- 28 single data transfer (ldr, str) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction encoding is shown in figure 3-14. the single data transfer instructions are used to load or store single bytes or words of data. the memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. the result of this calculation may be written back into the base register if auto-indexing is required. 31 27 19 15 0 cond 28 16 11 12 21 23 b 20 l rn rd 22 01 i p u offset w 26 24 25 [15:12] source/destination registers [19:16] base register [20] load/store bit 0 = store to memory 1 = load from memory [21] write-back bit 0 = no write-back 1 = write address into base [22] byte/word bit 0 = transfer word quantity 1 = transfer byte quantity [23] up/down bit 0 = down: subtract offset from base 1 = up: add offset to base [24] pre/post indexing bit 0 = post: add offset after transfer 1 = pre: add offset before transfer [25] immediate offset 0 = offset is an immediate value [11:0] offset shift immediate [11:0] unsigned 12-bit immediate offset 11 11 rm [3:0] offset register [11:4] shift applied to rm [31:28] condition field 0 4 3 0 figure 3-14. single data transfer instructions
s3c2400 risc microprocessor arm instruction set 3- 29 offsets and auto-indexing the offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). the offset may be added to (u=1) or subtracted from (u=0) the base register rn. the offset modification may be performed either before (pre-indexed, p=1) or after (post-indexed, p=0) the base is used as the transfer address. the w bit gives optional auto increment and decrement addressing modes. the modified base value may be written back into the base (w=1), or the old base value may be kept (w=0). in the case of post-indexed addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained by setting the offset to zero. therefore post-indexed data transfers always write back the modified base. the only use of the w bit in a post- indexed data transfer is in privileged mode code, where setting the w bit forces non-privileged mode for the transfer, allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware. shifted register offset the 8 shift control bits are described in the data processing instructions section. however, the register specified shift amounts are not available in this instruction class. see figure 3-5. bytes and words this instruction class may be used to transfer a byte (b=1) or a word (b=0) between an arm920t register and memory. the action of ldr(b) and str(b) instructions is influenced by the bigend control signal of arm920t core. the two possible configurations are described below. little- endian configuration a byte load (ldrb) expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary, on data bus inputs 15 through 8 if it is a word address plus one byte, and so on. the selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. please see figure 2-2. a byte store (strb) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. the external memory system should activate the appropriate byte subsystem to store the data. a word load (ldr) will normally use a word aligned address. however, an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7. this means that half- words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register. two shift operations are then required to clear or to sign extend the upper 16 bits. a word store (str) should generate a word aligned address. the word presented to the data bus is not affected if the address is not word aligned. that is, bit 31 of the register being stored always appears on data bus output 31.
arm instruction set s3c2400 risc micro processor 3- 30 ldr from word aligned address a+3 a a+2 a+1 memory 24 16 8 0 a b c d register 24 16 8 0 a b c d ldr from address offset by 2 a+3 a a+2 a+1 memory 24 16 8 0 a b c d register 24 16 8 0 a b c d figure 3-15. little- endian offset addressing big- endian configuration a byte load (ldrb) expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. the selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros. please see figure 2-1. a byte store (strb) repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0. the external memory system should activate the appropriate byte subsystem to store the data. a word load (ldr) should generate a word aligned address. an address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24. this means that half-words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register. a shift operation is then required to move (and optionally sign extend) the data into the bottom 16 bits. an address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8. a word store (str) should generate a word aligned address. the word presented to the data bus is not affected if the address is not word aligned. that is, bit 31 of the register being stored always appears on data bus output 31.
s3c2400 risc microprocessor arm instruction set 3- 31 use of r15 write-back must not be specified if r15 is specified as the base register ( rn). when using r15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction. r15 must not be specified as the register offset ( rm). when r15 is the source register (rd) of a register store (str) instruction, the stored value will be address of the instruction plus 12. restriction on the use of base register when configured for late aborts, the following example code is difficult to unwind as the base register, rn, gets updated before the abort handler starts. sometimes it may be impossible to calculate the initial value. after an abort, the following example code is difficult to unwind as the base register, rn, gets updated before the abort handler starts. sometimes it may be impossible to calculate the initial value. example: ldr r0,[r1],r1 therefore a post-indexed ldr or str where rm is the same register as rn should not be used. data aborts a transfer to or from a legal address may cause problems for a memory management system. for instance, in a system which uses virtual memory the required data may be absent from main memory. the memory manager can signal a problem by taking the processor abort input high whereupon the data abort trap will be taken. it is up to the system software to resolve the cause of the problem, then the instruction can be restarted and the original program continued. instruction cycle times normal ldr instructions take 1s + 1n + 1i and ldr pc take 2s + 2n +1i incremental cycles, where s,n and i are defined as sequential (s-cycle), non-sequential (n-cycle), and internal (i-cycle), respectively. str instructions take 2n incremental cycles to execute.
arm instruction set s3c2400 risc micro processor 3- 32 assembler syntax { cond}{b}{t} rd,

where: ldr load from memory into a register str store from a register into memory { cond} two-character condition mnemonic. see table 3-2. {b} if b is present then byte transfer, otherwise word transfer {t} if t is present the w bit will be set in a po st-indexed instruction, forcing non-privileged mode for the transfer cycle. t is not allowed when a pre-indexed addressing mode is specified or implied. rd an expression evaluating to a valid register number. rn and rm expressions evaluating to a register number. if rn is r15 then the assembler will subtract 8 from the offset value to allow for arm920t pipelining. in this case base write-back should not be specified.

ldr load from memor y into a register str store from a register into memory { cond} two-character condition mnemonic. see table 3-2.. h transfer halfword quantity sb load sign extended byte (only valid for ldr) sh load sign extended halfword (only valid for ldr) rd an expression evaluating to a valid register number.

ldc load from memory to coprocessor stc store from coprocessor to memory {l} when present perform long transfer (n=1), otherwise perform short transfer (n=0) { cond} two character condition mn emonic. see table 3-2.. p# the unique number of the required coprocessor cd an expression evaluating to a valid coprocessor register number that is placed in the crd field

can be: 1 an expression which generates an address: the assembler will attempt to generate an instruction using the pc as a base and a corrected immediate offset to address the location given by evaluating the expression. this will be a pc relative, pre-indexed address. if the address is out of range, an error will be generated 2 a pre-indexed addressing specification: [ rn] offset of zero [ rn,<#expression>]{!} offset of bytes 3 a post-indexed addressing specification: [ rn],<#expression offset of bytes {!} write back the base register (set the w bit) if! is present rn is an expression evaluating to a valid arm920t register number. notes if rn is r15, the assembler will subtract 8 from the offset value to allow for arm920t pipelining. examples ldc p1,c2,table ; load c2 of coproc 1 from address ; table, using a pc relative address. stceql p2,c3,[r5,#24]! ; conditionally store c3 of coproc 2 ; into an address 24 bytes up from r5, ; write this address back to r5, and use ; long transfer option (probably to store multiple words). notes although the address offset is expressed in bytes, the instruction offset field is in words. the assembler will adjust the offset appropriately.
arm instruction set s3c2400 risc micro processor 3- 56 coprocessor register transfers (mrc, mcr) the instruction is only executed if the condition is true. the various conditions are defined in table 3-2.. the instruction encoding is shown in figure 3-27. this class of instruction is used to communicate information directly between arm920t and a coprocessor. an example of a coprocessor to arm920t register transfer (mrc) instruction would be a fix of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to arm920t register. a float of a 32 bit value in arm920t register into a floating point value within the coprocessor illustrates the use of arm920t register to coprocessor transfer (mcr). an important use of this instruction is to communicate control information directly from the coprocessor into the arm920t cpsr flags. as an example, the result of a comparison of two floating point values within a coprocessor can be moved to the cpsr to control the subsequent flow of execution. 31 27 19 15 cond 28 16 11 12 21 23 20 l crn rd [3:0] coprocessor operand register [7:5] coprocessor information [11:8] coprocessor number [15:12] arm source/destination register [19:16] coprocessor source/destination register [20] load/store bit 0 = store to coprocessor 1 = load from coprocessor [21] coprocessor operation mode [31:28] condition field 1110 cp opc cp# 24 crm 1 cp 8 7 5 4 3 0 figure 3-27. coprocessor register transfer instructions the coprocessor fields the cp# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon. the cp opc, crn, cp and crm fields are used only by the coprocessor, and the interpretation presented here is derived from convention only. other interpretations are allowed where the coprocessor functionality is incompatible with this one. the conventional interpretation is that the cp opc and cp fields specify the operation the coprocessor is required to perform, crn is the coprocessor register which is the source or destination of the transferred information, and crm is a second coprocessor register which may be involved in some way which depends on the particular operation specified.
s3c2400 risc microprocessor arm instruction set 3- 57 transfers to r15 when a coprocessor register transfer to arm920t has r15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the n, z, c and v flags respectively. the other bits of the transferred word are ignored, and the pc and other cpsr bits are unaffected by the transfer. transfers from r15 a coprocessor register transfer from arm920t with r15 as the source register will store the pc+12. instruction cycle times mrc instructions take 1s + (b+1)i +1c incremental cycles to execute, where s, i and c are defined as sequential (s-cycle), internal (i-cycle), and coprocessor register transfer (c-cycle), respectively. mcr instructions take 1s + bi +1c incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. assembler syntax { cond} p#,,rd,cn,cm{,} mrc move from coprocessor to arm920t register (l=1) mcr move from arm920t register to coprocessor (l=0) { cond} tw o character condition mnemonic. see table 3-2 p# the unique number of the required coprocessor evaluated to a constant and placed in the cp opc field rd an expression evaluating to a valid arm920t register number cn and cm expressi ons evaluating to the valid coprocessor register numbers crn and crm respectively where present is evaluated to a constant and placed in the cp field examples mrc p2,5,r3,c5,c6 ; request coproc 2 to perform operation 5 ; on c5 and c6, and transfer the (single ; 32-bit word) result back to r3. mcr p6,0,r4,c5,c6 ; request coproc 6 to perform operation 0 ; on r4 and place the result in c6. mrceq p3,9,r3,c5,c6,2 ; conditionally request coproc 3 to ; perform operation 9 (type 2) on c5 and ; c6, and transfer the result back to r3.
arm instruction set s3c2400 risc micro processor 3- 58 undefined instruction the instruction is only executed if the condition is true. the various conditions are defined in table 3-2. the instruction format is shown in figure 3-28. 31 27 cond 28 25 24 011 xxxxxxxxxxxxxxxxxxxx 1 xxxx 5 4 3 0 figure 3-28. undefined instruction if the condition is true, the undefined instruction trap will be taken. note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present, and all coprocessors must refuse to accept it by driving cpa and cpb high. instruction cycle times this instruction takes 2s + 1i + 1n cycles, where s, n and i are defined as sequential (s-cycle), non-sequential (n- cycle), and internal (i-cycle). assembler syntax the assembler has no mnemonics for generating this instruction. if it is adopted in the future for some specified use, suitable mnemonics will be added to the assembler. until such time, this instruction must not be used.
s3c2400 risc microprocessor arm instruction set 3- 59 instruction set examples the following examples show ways in which the basic arm920t instructions can combine to give efficient code. none of these methods saves a great deal of execution time (although they may save some), mostly they just save code. using the conditional instructions using conditionals for logical or cmp rn,#p ; if rn=p or rm=q then goto label. beq label cmp rm,#q beq label this can be replaced by cmp rn,#p cmpne rm,#q ; if condition not satisfied try other test. beq label absolute value teq rn,#0 ; test sign rsbmi rn,rn,#0 ; and 2's complement if necessary. multiplication by 4, 5 or 6 (run time) mov rc,ra,lsl#2 ; multiply by 4, cmp rb,#5 ; test value, addcs rc,rc,ra ; complete multiply by 5, addhi rc,rc,ra ; complete multiply by 6. combining discrete and range tests teq rc,#127 ; discrete test, cmpne rc,# " "-1 ; range test movls rc,# "" ; if rc<= "" or rc=ascii(127) ; then rc:= "."
arm instruction set s3c2400 risc micro processor 3- 60 division and remainder a number of divide routines for specific applications are provided in source form as part of the ansi c library provided with the arm cross development toolkit, available from your supplier. a short general purpose divide routine follows. ; enter with numbers in ra and rb. mov rcnt,#1 ; bit to control the division. div1 cmp rb,#0x80000000 ; mo ve rb until greater than ra. cmpcc rb,ra movcc rb,rb,asl#1 movcc rcnt,rcnt,asl#1 bcc div1 mov rc,#0 div2 cmp ra,rb ; test for possible subtraction. subcs ra,ra,rb ; subtract if ok, addcs rc,rc,rcnt ; put relevant bit into result movs rcnt,rcnt,lsr #1 ; shift control bit movne rb,rb,lsr#1 ; halve unless finished. bne div2 ; divide result in rc, remainder in ra. overflow detection in the arm920t 1. overflow in unsigned multiply with a 32-bit result umull rd,rt,rm,rn ; 3 to 6 cycles teq rt,#0 ; + 1 cycle and a register bne overflow 2. overflow in signed multiply with a 32-bit result smull rd,rt,rm,rn ; 3 to 6 cycles teq rt,rd asr#31 ; +1 cycle and a register bne overflow 3. overflow in unsigned multiply accumulate with a 32 bit result umlal rd,rt,rm,rn ; 4 to 7 cycles teq rt,#0 ; +1 cycle and a register bne overflow 4. overflow in signed multiply accumulate with a 32 bit result smlal rd,rt,rm,rn ; 4 to 7 cycles teq rt,rd, asr#31 ; +1 cycle and a register bne overflow
s3c2400 risc microprocessor arm instruction set 3- 61 5. overflow in un signed multiply accumulate with a 64 bit result umull rl,rh,rm,rn ; 3 to 6 cycles adds rl,rl,ra1 ; lower accumulate adc rh,rh,ra2 ; upper accumulate bcs overflow ; 1 cycle and 2 registers 6. overflow in signed multiply accumulate with a 64 bit result smull rl,rh,rm,rn ; 3 to 6 cycles adds rl,rl,ra1 ; lower accumulate adc rh,rh,ra2 ; upper accumulate bvs overflow ; 1 cycle and 2 registers notes overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow does not occur in such calculations. pseudo-random binary sequence generator it is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-or feedback rather like a cyclic redundancy check generator. unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition), so this example uses a 33 bit register with taps at bits 33 and 20. the basic algorithm is newbit:=bit 33 eor bit 20, shift left the 33 bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e. 32 bits). the entire operation can be done in 5 s cycles: ; enter with seed in ra (32 bits), ; rb (1 bit in rb lsb), uses rc. tst rb,rb,lsr#1 ; top bit into carry movs rc,ra,rrx ; 33 bit rotate right adc rb,rb,rb ; carry into lsb of rb eor rc,rc,ra,lsl#12 ; (involved!) eor ra,rc,rc,lsr#20 ; (similarly involved!) new seed in ra, rb as before multiplication by constant using the barrel shifter multiplication by 2^n (1,2,4,8,16,32..) mov ra, rb, lsl #n multiplication by 2^n+1 (3,5,9,17..) add ra,ra,ra,lsl #n multiplication by 2^n-1 (3,7,15..) rsb ra,ra,ra,lsl #n
arm instruction set s3c2400 risc micro processor 3- 62 multiplication by 6 add ra,ra,ra,lsl #1 ; multiply by 3 mov ra,ra,lsl#1 ; and then by 2 multiply by 10 and add in extra number add ra,ra,ra,lsl#2 ; multiply by 5 add ra,rc,ra,lsl#1 ; multiply by 2 and add in next digit general recursive method for rb := ra*c, c a constant: 1. if c even, say c = 2^n*d, d odd: d=1: mov rb,ra,lsl #n d<>1: { rb := ra*d} mov rb,rb,lsl #n 2. if c mod 4 = 1, say c = 2^n*d+1, d odd, n>1: d=1: add rb,ra,ra,lsl #n d<>1: { rb := ra*d} add rb,ra,rb,lsl #n 3. if c mod 4 = 3, say c = 2^n*d-1, d odd, n>1: d=1: rsb rb,ra,ra,lsl #n d<>1: { rb := ra*d} rsb rb,ra,rb,lsl #n this is not quite optimal, but close. an example of its non-optimality is multiply by 45 which is done by: rsb rb,ra,ra,lsl#2 ; multiply by 3 rsb rb,ra,rb,lsl#2 ; multiply by 4*3-1 = 11 add rb,ra,rb,lsl# 2 ; multiply by 4*11+1 = 45 rather than by: add rb,ra,ra,lsl#3 ; multiply by 9 add rb,rb,rb,lsl#2 ; multiply by 5*9 = 45
s3c2400 risc microprocessor arm instruction set 3- 63 loading a word from an unknown alignment ; enter with address in ra (32 bits) uses ; rb, rc result in rd. note d must be less than c e.g. 0,1 bic rb,ra,#3 ; get word aligned address ldmia rb,{ rd,rc} ; get 64 bits containing answer and rb,ra,#3 ; correction factor in bytes movs rb,rb,lsl#3 ; ...now in bits and test if aligned movne rd,rd,lsr rb ; produce bottom of result word (if not aligned) rsbne rb,rb,#32 ; get other shift amount orrne rd,rd,rc,lsl rb ; combine two halves to get result
arm instruction set s3c2400 risc micro processor 3- 64 notes
S3C2400X01 risc microprocessor thumb instruction set 4 - 1 4 thumb instruction set thumb instruction set format the thumb instruction sets are 16-bit versions of arm instruction sets (32-bit format). the arm instructions are reduced to 16-bit versions, thumb instructions, at the cost of versatile functions of the arm instruction sets. the thumb instructions are decompressed to the arm instructions by the thumb decompressor inside the arm920t core. as the thumb instructions are compressed arm instructions, the thumb instructions have the 16-bit format instructions and have some restrictions. the restrictions by 16-bit format is fully notified for using the thumb instructions.
thumb instruction set S3C2400X01 risc microprocessor 4 - 2 format summary the thumb instruction set formats are shown in the following figure. move shifted register 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 l 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 l 1 0 r 1 1 0 1 0 sp 1 l l s h 0 0 1 b l 0 1 h 0 1 b 0 0 1 1 1 i op op op op op l 0 s 1 offset5 rs rd rn/offset3 rd rs rd offset8 rs rd/hd rd h1 h2 rs/hs rd word8 rd rb ro ro rb rd offset5 rb rd rb rd offset5 rd rd word8 word8 sword7 rb cond rlist rlist softset8 value8 offset11 offset add/subtract move/compare/add/ subtract immediate alu operations hi register operations /branch exchange pc-relative load load/store with register offset load/store with immediate offset load/store sign-extended byte/halfword load/store halfword sp-relative load/store load address add offset to stack pointer push/pop register multiple load/store conditional branch software interrupt unconditional branch long branch with link 15 14 13 12 11 10 9 8 7 6 5 4 2 3 1 0 15 14 13 12 11 10 9 8 7 6 5 4 2 3 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 figure 4- 1 . thumb instruction set formats
S3C2400X01 risc microprocessor thumb instruction set 4 - 3 opcode summary the following table summarizes the thumb instruction set. for further information about a particular instruction please refer to the sections listed in the right-most column. table 4- 1 . thumb instruction set opcodes mnemonic instruction lo-register operand hi-register operand condition codes set adc add with carry y - y add add y - y (1) and and y - y asr arithmetic shift right y - y b unconditional branch y - - bxx conditional branch y - - bic bit clear y - y bl branch and link - - - bx branch and exchange y y - cmn compare negative y - y cmp compare y y y eor eor y - y ldmia load multiple y - - ldr load word y - - ldrb load byte y - - ldrh load halfword y - - lsl logical shift left y - y ldsb load sign-extended byte y - - ldsh load sign-extended halfword y - - lsr logical shift right y - y mov move register y y y (2) mul multiply y - y mvn move negative register y - y
thumb instruction set S3C2400X01 risc microprocessor 4 - 4 table 4- 1 . thumb instruction set opcodes (continued) mnemonic instruction lo-register operand hi-register operand condition codes set neg negate y - y orr or y - y pop pop register y - - push push register y - - ror rotate right y - y sbc subtract with carry y - y stmia store multiple y - - str store word y - - strb store byte y - - strh store halfword y - - swi software interrupt - - - sub subtract y - y tst test bits y - y notes: 1. the condition codes are unaffected by the format 5, 12 and 13 versions of this instruction. 2. the condition codes are unaffected by the format 5 version of this instruction.
S3C2400X01 risc microprocessor thumb instruction set 4 - 5 format 1: move shifted register 15 0 0 14 10 [2:0] destination register [5:3] source register [10:6] immediate vale [12:11] opcode 0 = lsl 1 = lsr 2 = asr offset5 6 5 3 2 rd 0 0 13 12 11 op rs figure 4- 2 . format 1 operation these instructions move a shifted value between lo registers. the thumb assembler syntax is shown in table 4-2. note all instructions in this group set the cpsr condition codes. table 4-2. summary of format 1 instructions op thumb assembler arm equipment action 00 lsl rd, rs, #offset5 movs rd, rs, lsl #offset5 shift rs left by a 5-bit immediate value and store the result in rd. 01 lsr rd, rs, #offset5 movs rd, rs, lsr #offset5 perform logical shift right on rs by a 5-bit immediate value and store the result in rd. 10 asr rd, rs, #offset5 movs rd, rs, asr #offset5 perform arithmetic shift right on rs by a 5-bit immediate value and store the result in rd.
thumb instruction set S3C2400X01 risc microprocessor 4 - 6 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4-2. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples lsr r2, r5, #27 ; logical shift right the contents ; of r5 by 27 and store th e result in r2. ; set condition codes on the result.
S3C2400X01 risc microprocessor thumb instruction set 4 - 7 format 2: add/subtract 15 0 14 10 [2:0] destination register [5:3] source register [8:6] register/immediate vale [9] opcode 0 = add 1 = sub [10] immediate flag 0 = register operand 1 = immediate oerand rn/offset3 rd 0 0 13 12 11 op rs 9 8 1 1 1 6 5 3 2 0 figure 4-3. format 2 operation these instructions allow the contents of a lo register or a 3-bit immediate value to be added to or subtracted from a lo register. the thumb assembler syntax is shown in table 4-3. note all instructions in this group set the cpsr condition codes. table 4-3. summary of format 2 instructions op i thumb assembler arm equipment action 0 0 add rd, rs, rn adds rd, rs, rn add contents of rn to contents of rs. place result in rd. 0 1 add rd, rs, #offset3 adds rd, rs, #offset3 add 3-bit immediate value to contents of rs. place result in rd. 1 0 sub rd, rs, rn subs rd, rs, rn subtract contents of rn from contents of rs. place result in rd. 1 1 sub rd, rs, #offset3 subs rd, rs, #offset3 subtract 3-bit immediate value from contents of rs. place result in rd.
thumb instruction set S3C2400X01 risc microprocessor 4 - 8 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4-3. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add r0, r3, r4 ; r0 := r3 + r4 and set condition codes on the result. sub r6, r2, #6 ; r6 := r2 - 6 and set condition codes.
S3C2400X01 risc microprocessor thumb instruction set 4 - 9 format 3: move/compare/add/subtract immediate 15 0 0 14 10 [7:0] immediate vale [10:8] source/destination register [12:11] opcode 0 = mov 1 = cmp 2 = add 3 = sub offset8 rd 0 0 13 12 11 op 7 8 figure 4- 4 . format 3 operations the instructions in this group perform operations between a lo register and an 8-bit immediate value. the thumb assembler syntax is shown in table 4- 4 . note all instructions in this group set the cpsr condition codes. table 4- 4 . summary of format 3 instructions op thumb assembler arm equipment action 00 mov rd, #offset8 movs rd, #offset8 move 8-bit immediate value into rd. 01 cmp rd, #offset8 cmp rd, #offset8 compare contents of rd with 8-bit immediate value. 10 add rd, #offset8 adds rd, rd, #offset8 add 8-bit immediate value to contents of rd and place the result in rd. 11 sub rd, #offset8 subs rd, rd, #offset8 subtract 8-bit immediate value from contents of rd and place the result in rd.
thumb instruction set S3C2400X01 risc microprocessor 4 - 10 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 4 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples mov r0, #128 ; r0 := 128 and set condition codes cmp r2, #62 ; set condition codes on r2 - 62 add r1, #255 ; r1 := r1 + 255 and set condition codes sub r6, #145 ; r6 := r6 - 145 and set condition codes
S3C2400X01 risc microprocessor thumb instruction set 4 - 11 format 4: alu operations 15 0 0 14 10 [2:0] source/destination register [5:3] source register 2 [9:6] opcode 5 6 3 rd 0 0 13 12 11 op rs 0 0 0 9 2 figure 4- 5 . format 4 operation the following instructions perform alu operations on a lo register pair. note all instructions in this group set the cpsr condition codes. table 4- 5 . summary of format 4 instructions op thumb assembler arm equipment action 0000 and rd, rs ands rd, rd, rs rd:= rd and rs 0001 eor rd, rs eors rd, rd, rs rd:= rd eor rs 0010 lsl rd, rs movs rd, rd, lsl rs rd := rd << rs 0011 lsr rd, rs movs rd, rd, lsr rs rd := rd >> rs 0100 asr rd, rs movs rd, rd, asr rs rd := rd asr rs 0101 adc rd, rs adcs rd, rd, rs rd := rd + rs + c-bit 0110 sbc rd, rs sbcs rd, rd, rs rd := rd - rs - not c-bit 0111 ror rd, rs movs rd, rd, ror rs rd := rd ror rs 1000 tst rd, rs tst rd, rs set condition codes on rd and rs 1001 neg rd, rs rsbs rd, rs, #0 rd = - rs 1010 cmp rd, rs cmp rd, rs set condition codes on rd - rs 1011 cmn rd, rs cmn rd, rs set condition codes on rd + rs 1100 orr rd, rs orrs rd, rd, rs rd := rd or rs 1101 mul rd, rs muls rd, rs, rd rd := rs * rd 1110 bic rd, rs bics rd, rd, rs rd := rd and not rs 1111 mvn rd, rs mvns rd, rs rd := not rs
thumb instruction set S3C2400X01 risc microprocessor 4 - 12 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 5 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples eor r3, r4 ; r3 := r3 eor r4 and set condition codes ror r1, r0 ; rotate right r1 by the value in r0, store ; the result in r1 and set condition codes neg r5, r3 ; sub tract the contents of r3 from zero, ; store the result in r5. set condition codes ie r5 = - r3 cmp r2, r6 ; set the condition codes on the result of r2 - r6 mul r0, r7 ; r0 := r7 * r0 and set condition codes
S3C2400X01 risc microprocessor thumb instruction set 4 - 13 format 5: hi-register operations/branch exchange 15 0 0 14 10 [2:0] destination register [5:3] source register [6] hi operand flag 2 [7] hi operand flag 1 [9:8] opcode 6 5 3 2 rd/hd 0 0 13 12 11 op rs/hs 0 0 0 9 8 7 h1 h2 figure 4- 6 . format 5 operation there are four sets of instructions in this group. the first three allow add, cmp and mov operations to be performed between lo and hi registers, or a pair of hi registers. the fourth, bx, allows a branch to be performed which may also be used to switch processor state. the thumb assembler syntax is shown in table 4- 6 . note in this group only cmp (op = 01) sets the cpsr condition codes. the action of h1= 0, h2 = 0 for op = 00 (add), op =01 (cmp) and op = 10 (mov) is undefined, and should not be used. table 4- 6 . summary of format 5 instructions op h1 h2 thumb assembler arm equivalent action 00 0 1 add rd, hs add rd, rd, hs add a register in the range 8-15 to a register in the range 0-7. 00 1 0 add hd, rs add hd, hd, rs add a register in the range 0-7 to a register in the range 8-15. 00 1 1 add hd, hs add hd, hd, hs add two registers in the range 8-15 01 0 1 cmp rd, hs cmp rd, hs compare a register in the range 0-7 with a register in the range 8-15. set the condition code flags on the result. 01 1 0 cmp hd, rs cmp hd, rs compare a register in the range 8-15 with a register in the range 0-7. set the condition code flags on the result.
thumb instruction set S3C2400X01 risc microprocessor 4 - 14 table 4- 6 . summary of format 5 instructions (continued) op h1 h2 thumb assembler arm equivalent action 01 1 1 cmp hd, hs cmp hd, hs compare two registers in the range 8-15. set the condition code flags on the result. 10 0 1 mov rd, hs mov rd, hs move a value from a register in the range 8-15 to a register in the range 0- 7. 10 1 0 mov hd, rs mov hd, rs move a value from a register in the range 0-7 to a register in the range 8-15. 10 1 1 mov hd, hs mov hd, hs move a value between two registers in the range 8-15. 11 0 0 bx rs bx rs perform branch (plus optional state change) to address in a register in the range 0-7. 11 0 1 bx hs bx hs perform branch (plus optional state change) to address in a register in the range 8-15. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 6 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. the bx instruction bx performs a branch to a routine whose start address is specified in a lo or hi register. bit 0 of the address determines the processor state on entry to the routine: bit 0 = 0 causes the processor to enter arm state. bit 0 = 1 causes the processor to enter thumb state. note the action of h1 = 1 for this instruction is undefined, and should not be used.
S3C2400X01 risc microprocessor thumb instruction set 4 - 15 examples hi-register operations add pc, r5 ; pc := pc + r5 but don't set the condition codes. cmp r4, r12 ; set the condition codes on the result of r4 - r12. mov r15, r14 ; move r14 (lr) into r15 (pc) ; but don't set the condition codes, ; eg. return from subroutine. branch and exchange ; switch from thumb to arm state. adr r1,outofthumb ; load address of outofthumb into r1. mov r11,r1 bx r11 ; transfer the contents of r11 into the pc. ; bit 0 of r11 determines whether ; arm or thumb state is entered, ie. arm state here. align code32 outofthumb ; now processing arm instructions... using r15 as an operand if r15 is used as an operand, the value will be the address of the instruction + 4 with bit 0 cleared. executing a bx pc in thumb state from a non-word aligned address will result in unpredictable execution.
thumb instruction set S3C2400X01 risc microprocessor 4 - 16 format 6: pc-relative load 15 0 0 14 10 [7:0] immediate value [10:8] destination register word 8 0 0 13 12 11 rd 0 0 8 7 figure 4- 7 . format 6 operation this instruction loads a word from an address specified as a 10-bit immediate offset from the pc. the thumb assembler syntax is shown below. table 4- 7 . summary of pc-relative load instruction thumb assembler arm equivalent action ldr rd, [pc, #imm] ldr rd, [r15, #imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the pc. load the word from the resulting address into rd. note : the value specified by #imm is a full 10-bit address, bu t must always be word-aligned (ie with bits 1:0 set to 0), since the assembler places #imm >> 2 in field word 8. the value of the pc will be 4 bytes greater than the address of this instruction, but bit 1 of the pc is forced to 0 to ensure it is word aligned.
S3C2400X01 risc microprocessor thumb instruction set 4 - 17 instruction cycle times all instructions in this format have an equivalent arm instruction. the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples ldr r3,[pc,#844] ; load into r3 the word found at the ; address formed by adding 844 to pc. ; bit[1] of pc is forced to zero. ; note that the thumb opcode will contain ; 211 as the word8 value.
thumb instruction set S3C2400X01 risc microprocessor 4 - 18 format 7: load/store with register offset [2:0] source/destination register [5:3] base register [8:6] offset register [10] byte/word flag 0 = transfer word quantity 1 = transfer byte quantity [11] load/store flag 0 = store to memory 1 = load from memory 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 1 l b 9 8 ro 0 figure 4- 8 . format 7
S3C2400X01 risc microprocessor thumb instruction set 4 - 19 operation these instructions transfer byte or word values between registers and memory. memory addresses are pre-indexed using an offset register in the range 0-7. the thumb assembler syntax is shown in table 4- 8 . table 4- 8 . summary of format 7 instructions l b thumb assembler arm equivalent action 0 0 str rd, [rb, ro] str rd, [rb, ro] pre-indexed word store: calculate the target address by adding together the value in rb and the value in ro. store the contents of rd at the address. 0 1 strb rd, [rb, ro] strb rd, [rb, ro] pre-indexed byte store: calculate the target address by adding together the value in rb and the value in ro. store the byte value in rd at the resulting address. 1 0 ldr rd, [rb, ro] ldr rd, [rb, ro] pre-indexed word load: calculate the source address by adding together the value in rb and the value in ro. load the contents of the address into rd. 1 1 ldrb rd, [rb, ro] ldrb rd, [rb, ro] pre-indexed byte load: calculate the source address by adding together the value in rb and the value in ro. load the byte value at the resulting address. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 8 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples str r3, [r2,r6] ; store word in r3 at the address ; formed by adding r6 to r2. ldrb r2, [r0,r7] ; load into r2 the byte found at ; the address formed by adding r7 to r0.
thumb instruction set S3C2400X01 risc microprocessor 4 - 20 format 8: load/store sign-extended byte/halfword [2:0] destination register [5:3] base register [8:6] offset register [10] sign-extended flag 0 = operand not sing-extended 1 = operand sing-extended [11] h flag 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 1 h s 9 8 ro 1 figure 4- 9 . format 8 operation these instructions load optionally sign-extended bytes or halfwords, and store halfwords. the thumb assembler syntax is shown below. table 4- 9 . summary of format 8 instructions l b thumb assembler arm equivalent action 0 0 strh rd, [rb, ro] strh rd, [rb, ro] store halfword: add ro to base address in rb. store bits 0-15 of rd at the resulting address. 0 1 ldrh rd, [rb, ro] ldrh rd, [rb, ro] load halfword: add ro to base address in rb. load bits 0-15 of rd from the resulting address, and set bits 16-31 of rd to 0. 1 0 ldsb rd, [rb, ro] ldrsb rd, [rb, ro] load sign-extended byte: add ro to base address in rb. load bits 0-7 of rd from the resulting address, and set bits 8-31 of rd to bit 7. 1 1 ldsh rd, [rb, ro] ldrsh rd, [rb, ro] load sign-extended halfword: add ro to base address in rb. load bits 0-15 of rd from the resulting address, and set bits 16-31 of rd to bit 15.
S3C2400X01 risc microprocessor thumb instruction set 4 - 21 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 9 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples strh r4, [r3, r0] ; store the lower 16 bits of r4 at the ; address formed by adding r0 to r3. ldsb r2, [r7, r1] ; load into r2 the sign extended byte ; found at the address formed by adding r1 to r7. ldsh r3, [r4, r2] ; load into r3 the sign extended halfword ; found at the address formed by adding r2 to r4.
thumb instruction set S3C2400X01 risc microprocessor 4 - 22 format 9: load/store with immediate offset [2:0] source/destination register [5:3] base register [10:6] offset register [11] load/store flag 0 = store to memory 1 = load from memory [12] byte/word flad 0 = transfer word quantity 1 = transfer byte quantity 15 0 0 14 10 6 5 3 2 rd 1 1 13 12 11 rb b l offset5 figure 4- 10 . format 9
S3C2400X01 risc microprocessor thumb instruction set 4 - 23 operation these instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset. the thumb assembler syntax is shown in table 4- 10 . table 4- 10 . summary of format 9 instructions l b thumb assembler arm equivalent action 0 0 str rd, [rb, #imm] str rd, [rb, #imm] calculate the target address by adding together the value in rb and imm. store the contents of rd at the address. 1 0 ldr rd, [rb, #imm] ldr rd, [rb, #imm] calculate the source address by adding together the value in rb and imm. load rd from the address. 0 1 strb rd, [rb, #imm] strb rd, [rb, #imm] calculate the target address by adding together the value in rb and imm. store the byte value in rd at the address. 1 1 ldrb rd, [rb, #imm] ldrb rd, [rb, #imm] calculate source address by adding together the value in rb and imm. load the byte value at the address into rd. note : for word accesses (b = 0), the value specified by #imm is a full 7-bit address, but mus t be word-aligned (ie with bits 1:0 set to 0), since the assembler places #imm >> 2 in the offset5 field. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 10 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples ldr r2, [r5,#116] ; load into r2 the word found at the ; address formed by adding 116 to r5. ; note that the thumb opcode will ; contain 29 as the offset5 val ue. strb r1, [r0,#13] ; store the lower 8 bits of r1 at the ; address formed by adding 13 to r0. ; note that the thumb opcode will ; contain 13 as the offset5 value.
thumb instruction set S3C2400X01 risc microprocessor 4 - 24 format 10: load/store halfword [2:0] source/destination register [5:3] base register [10:6] immediate value [11] load/store flag 0 = store to memory 1 = load from memory 15 0 0 14 10 6 5 3 2 rd 1 0 13 12 11 rb 0 l offset5 figure 4- 11 . format 10 operation these instructions transfer halfword values between a lo register and memory. addresses are pre-indexed, using a 6-bit immediate value. the thumb assembler syntax is shown in table 4- 11 . table 4- 11 . halfword data transfer instructions l thumb assembler arm equivalent action 0 strh rd, [rb, #imm] strh rd, [rb, #imm] add #imm to base address in rb and store bits 0 - 15 of rd at the resulting address. 1 ldrh rd, [rb, #imm] ldrh rd, [rb, #imm] add #imm to base address in rb. load bits 0-15 from the resulting address into rd and set bits 16-31 to zero. note : #imm is a full 6-bit address but must be halfword-aligned (ie with bit 0 set to 0) si nce the assembler places #imm >> 1 in the offset5 field.
S3C2400X01 risc microprocessor thumb instruction set 4 - 25 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 11 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples strh r6, [r1, #56] ; store the lower 16 bits of r4 at the address formed by ; adding 56 r1. note that the thumb opcode will contain ; 28 as the offset5 value. ldrh r4, [r7, #4] ; load into r4 the halfword fo und at the address formed by ; adding 4 to r7. note that the thumb opcode will contain ; 2 as the offset5 value.
thumb instruction set S3C2400X01 risc microprocessor 4 - 26 format 11: sp-relative load/store [7:0] immediate value [10:8] destination register [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 0 0 13 12 11 word 8 1 l rd 7 8 figure 4- 12 . format 11 operation the instructions in this group perform an sp-relative load or store. the thumb assembler syntax is shown in the following table. table 4- 12 . sp-relative load/store instructions l thumb assembler arm equivalent action 0 str rd, [sp, #imm] str rd, [r13 #imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the sp (r7). store the contents of rd at the resulting address. 1 ldr rd, [sp, #imm] ldr rd, [r13 #imm] add unsigned offset (255 words, 1020 bytes) in imm to the current value of the sp (r7). load the word from the resulting address into rd. note : the offset supplied in #imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0), since the a ssembler places #imm >> 2 in the word8 field.
S3C2400X01 risc microprocessor thumb instruction set 4 - 27 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 12 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples str r4, [sp,#492] ; store the contents of r4 at the address ; formed by adding 492 to sp (r13). ; note that the thumb opcode will contain ; 123 as the word8 value.
thumb instruction set S3C2400X01 risc microprocessor 4 - 28 format 12: load address [7:0] 8-bit unsigned constant [10:8] destination register [11] source 0 = pc 1 = sp 15 0 1 14 10 0 1 13 12 11 word 8 0 sp rd 7 8 figure 4- 13 . format 12 operation these instructions calculate an address by adding an 10-bit constant to either the pc or the sp, and load the resulting address into a register. the thumb assembler syntax is shown in the following table. table 4- 13 . load address l thumb assembler arm equivalent action 0 add rd, pc, #imm add rd, r15, #imm add #imm to the current value of the program counter (pc) and load the result into rd. 1 add rd, sp, #imm add rd, r13, #imm add #imm to the current value of the stack pointer (sp) and load the result into rd. note : the value specified by #imm is a full 10-bit value, but this must be word-aligned (ie with bits 1:0 set to 0) since the assembler places #imm >> 2 in field word 8. where the pc is used as the source register (sp = 0), bit 1 of the pc is always read as 0. the value of the pc will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0. the cpsr condition codes are unaffected by these instructions.
S3C2400X01 risc microprocessor thumb instruction set 4 - 29 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 13 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add r2, pc, #572 ; r2 := pc + 572, but don't set t he ; condition codes. bit[1] of pc is forced to zero. ; note that the thumb opcode will ; contain 143 as the word8 value. add r6, sp, #212 ; r6 := sp (r13) + 212, but don't ; set the condition codes. ; note that the thumb opcode will ; contain 53 as the word 8 value.
thumb instruction set S3C2400X01 risc microprocessor 4 - 30 format 13: add offset to stack pointer [6:0] 7-bit immediate value [7] sign flag 0 = offset is positive 1 = offset is negative 15 0 1 14 10 0 1 13 12 11 sword 7 1 0 0 7 8 9 6 0 0 s figure 4- 14 . format 13 operation this instruction adds a 9-bit signed constant to the stack pointer. the following table shows the thumb assembler syntax. table 4- 14 . the add sp instruction l thumb assembler arm equivalent action 0 add sp, #imm add r13, r13, #imm add #imm to the stack pointer (sp). 1 add sp, # -imm sub r13, r13, #imm add #-imm to the stack pointer (sp). note: the offset specified by #imm can be up to -/+ 508, but must be word-aligned (ie with bits 1:0 set to 0) since the assembler converts #imm to an 8-bit sign + magnitude number before placing it in field sword7. the condition codes are not set by this instruction. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 14 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples add sp, #268 ; sp (r13) := sp + 268, but don't set the condition codes. ; note that the thumb opcode will ; contain 67 as the word7 value and s=0. add sp, #-104 ; sp (r13) := sp - 104, but don't set the condition codes. ; note that the thumb opcode will contain ; 26 as the word7 value and s=1.
S3C2400X01 risc microprocessor thumb instruction set 4 - 31 format 14: push/pop registers [7:0] register list [8] pc/lr bit 0 = do not store lr/load pc 1 = store lr/load pc [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 0 1 13 12 11 rlist 1 l 0 7 8 9 1 r figure 4- 15 . format 14 operation the instructions in this group allow registers 0-7 and optionally lr to be pushed onto the stack, and registers 0-7 and optionally pc to be popped off the stack. the thumb assembler syntax is shown in table 4- 15 . note the stack is always assumed to be full descending. table 4- 15 .?push and pop instructions l b thumb assembler arm equivalent action 0 0 push { rlist } stmdb r13!, { rlist } push the registers specified by rlist onto the stack. update the stack pointer. 0 1 push { rlist, lr } stmdb r13!, { rlist, r14 } push the link register and the registers specified by rlist (if any) onto the stack. update the stack pointer. 1 0 pop { rlist } ldmia r13!, { rlist } pop values off the stack into the registers specified by rlist. update the stack pointer. 1 1 pop { rlist, pc } ldmia r13!, {rlist, r15} pop values off the stack and load into the registers specified by rlist. pop the pc off the stack. update the stack pointer.
thumb instruction set S3C2400X01 risc microprocessor 4 - 32 instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 15 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples push {r0-r4,lr} ; store r0,r1,r2,r3,r4 and r14 (lr) at ; the stack pointed to by r13 (sp) and update r13. ; useful at start of a sub-routine to ; save workspace and re turn address. pop {r2,r6,pc} ; load r2,r6 and r15 (pc) from the stack ; pointed to by r13 (sp) and update r13. ; useful to restore workspace and return from sub-routine.
S3C2400X01 risc microprocessor thumb instruction set 4 - 33 format 15: multiple load/store [7:0] register list [10:8] base register [11] load/store bit 0 = store to memory 1 = load from memory 15 0 1 14 10 1 0 13 12 11 rlist 0 l 7 8 rb figure 4- 16 . format 15 operation these instructions allow multiple loading and storing of lo registers. the thumb assembler syntax is shown in the following table. table 4- 16 . the multiple load/store instructions l thumb assembler arm equivalent action 0 stmia rb!, { rlist } stmia rb!, { rlist } store the registers specified by rlist, starting at the base address in rb. write back the new base address. 1 ldmia rb!, { rlist } ldmia rb!, { rlist } load the registers specified by rlist, starting at the base address in rb. write back the new base address. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 16 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples stmia r0!, {r3-r7} ; store the contents of registers r3-r7 ; starting at the address specified in ; r0, incrementing the addresses for each word. ; write back the updated value of r0.
thumb instruction set S3C2400X01 risc microprocessor 4 - 34 format 16: conditional branch [7:0] 8-bit signed immediate [11:8] condition 15 0 1 14 1 0 13 12 11 soffset 8 1 7 8 cond figure 4- 17 . format 16 operation the instructions in this group all perform a conditional branch depending on the state of the cpsr condition codes. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction. the thumb assembler syntax is shown in the following table. table 4 - 17 . the conditional branch instructions l thumb assembler arm equivalent action 0000 beq label beq label branch if z set (equal) 0001 bne label bne label branch if z clear (not equal) 0010 bcs label bcs label branch if c set (unsigned higher or same) 0011 bcc label bcc label branch if c clear (unsigned lower) 0100 bmi label bmi label branch if n set (negative) 0101 bpl label bpl label branch if n clear (positive or zero) 0110 bvs label bvs label branch if v set (overflow) 0111 bvc label bvc label branch if v clear (no overflow) 1000 bhi label bhi label branch if c set and z clear (unsigned higher)
S3C2400X01 risc microprocessor thumb instruction set 4 - 35 table 4 - 17 . the conditional branch instructions (continued) l thumb assembler arm equivalent action 1001 bls label bls label branch if c clear or z set (unsigned lower or same) 1010 bge label bge label branch if n set and v set, or n clear and v clear (greater or equal) 1011 blt label blt label branch if n set and v clear, or n clear and v set (less than) 1100 bgt label bgt label branch if z clear, and either n set and v set or n clear and v clear (greater than) 1101 ble label ble label branch if z set, or n set and v clear, or n clear and v set (less than or equal) notes 1. while label specifies a full 9-bit two's complement address, this must always be halfword-aligned (ie with bit 0 set to 0) since the assembler actually pla ces label >> 1 in field soffset8. 2. cond = 1110 is undefined, and should not be used. cond = 1111 creates the swi instruction: see . instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 3 - 1 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples cmp r0, #45 ; branch to over-if r0 > 45. bgt over ; note that the thumb opcode will contain ; the number of halfwords to offset. over ; must be halfword aligned.
thumb instruction set S3C2400X01 risc microprocessor 4 - 36 format 17: software interrupt [7:0] comment field 15 0 1 14 1 0 13 12 11 value 8 1 7 8 10 9 1 1 1 1 figure 4- 18 . format 17 operation the swi instruction performs a software interrupt. on taking the swi, the processor switches into arm state and enters supervisor (svc) mode. the thumb assembler syntax for this instruction is shown below. table 4- 18 . the swi instruction thumb assembler arm equivalent action swi value 8 swi value 8 perform software interrupt: move the address of the next instruction into lr, move cpsr to spsr, load the swi vector address (0x8) into the pc. switch to arm state and enter svc mode. note: value8 is used solely by the swi handler; it is ignored by the processor. instruction cycle times all instructions in this format have an equivalent arm instruction as shown in table 4- 18 . the instruction cycle times for the thumb instruction are identical to that of the equivalent arm instruction. examples swi 18 ; take the s oftware interrupt exception. ; enter supervisor mode with 18 as the ; requested swi number.
S3C2400X01 risc microprocessor thumb instruction set 4 - 37 format 18: unconditional branch [10:0] immediate value 15 0 1 14 1 1 13 12 11 offset11 0 10 0 figure 4- 19 . format 18 operation this instruction performs a pc-relative branch. the thumb assembler syntax is shown below. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction. table 4- 19 . summary of branch instruction thumb assembler arm equivalent action b label bal label (halfword offset) branch pc relative +/- offset11 << 1, where label is pc +/- 2048 bytes. note: the address specified by label is a full 12-bit two's complement address, but must always be halfword aligned (ie bit 0 set to 0), since the assembler places label >> 1 in the offset11 field. examples here b here ; branch onto itself. assembles to 0xe7fe. ; (note effect of pc offset). b jimmy ; branch to 'jimmy'. ; note that the thumb opcode will contain the number of ; halfwords to offset. jimmy ; must be halfword aligned.
thumb instruction set S3C2400X01 risc microprocessor 4 - 38 format 19: long branch with link [10:0] long branch and link offset high/low [11] low/high offset bit 0 = offset high 1 = offset low 15 0 1 14 1 1 13 12 11 offset 1 10 h figure 4- 20 . format 19 operation this format specifies a long branch with link. the assembler splits the 23-bit two's complement half-word offset specified by the label into two 11-bit halves, ignoring bit 0 (which must be 0), and creates two thumb instructions. instruction 1 (h = 0) in the first instruction the offset field contains the upper 11 bits of the target address. this is shifted left by 12 bits and added to the current pc address. the resulting address is placed in lr. instruction 2 (h =1) in the second instruction the offset field contains an 11-bit representation lower half of the target address. this is shifted left by 1 bit and added to lr. lr, which now contains the full 23-bit address, is placed in pc, the address of the instruction following the bl is placed in lr and bit 0 of lr is set. the branch offset must take account of the prefetch operation, which causes the pc to be 1 word (4 bytes) ahead of the current instruction
S3C2400X01 risc microprocessor thumb instruction set 4 - 39 instruction cycle times this instruction format does not have an equivalent arm instruction. table 4- 20 . the bl instruction l thumb assembler arm equivalent action 0 bl label none lr := pc + offsethigh << 12 1 temp := next instruction address pc := lr + offsetlow << 1 lr := temp | 1 examples bl faraway ; unconditionally branch to 'faraway' next ; and place following instruction ; address, ie "next", in r14,the link ; register and set bit 0 of lr high. ; note that the thumb opcodes will ; contain the number of halfwords to offset. faraway ; must be half-word aligned.
thumb instruction set S3C2400X01 risc microprocessor 4 - 40 instruction set examples the following examples show ways in which the thumb instructions may be used to generate small and efficient code. each example also shows the arm equivalent so these may be compared. multiplication by a constant using shifts and adds the following shows code to multiply by various constants using 1, 2 or 3 thumb instructions alongside the arm equivalents. for other constants it is generally better to use the built-in mul instruction rather than using a sequence of 4 or more instructions. thumb arm 1. multiplication by 2^n (1,2,4,8,...) lsl ra, rb, lsl #n ; mov ra, rb, lsl #n 2. multiplication by 2^n+1 (3,5,9,17,...) lsl rt, rb, #n ; add ra, rb, rb, lsl #n add ra, rt, rb 3. multiplication by 2^n-1 (3,7,15,...) lsl rt, rb, #n ; rsb ra, rb, rb, lsl #n sub ra, rt, rb 4. multiplication by -2^n (-2, -4, -8, ...) lsl ra, rb, #n ; mov ra, rb, lsl #n mvn ra, ra ; rsb ra, ra, #0 5. multiplication by -2^n-1 (-3, -7, -15, ...) lsl rt, rb , #n ; sub ra, rb, rb, lsl #n sub ra, rb, rt multiplication by any c = {2^n+1, 2^n-1, -2^n or -2^n-1} * 2^n effectively this is any of the multiplications in 2 to 5 followed by a final shift. this allows the following additional constants to be multiplied. 6, 10, 12, 14, 18, 20, 24, 28, 30, 34, 36, 40, 48, 56, 60, 62 ..... (2..5) ; (2..5) lsl ra, ra, #n ; mov ra, ra, lsl #n
S3C2400X01 risc microprocessor thumb instruction set 4 - 41 general purpose signed divide this example shows a general purpose signed divide and remainder routine in both thumb and arm code. thumb code ;signed_divide ; signed divide of r1 by r0: returns quotient in r0, ; remainder in r1 ;get abs value of r0 into r3 asr r2, r0, #31 ; get 0 or -1 in r2 depending on sign of r0 eor r0, r2 ; eor with -1 (0 ffffffff) if negative sub r3, r0 , r2 ; and add 1 (sub -1) to get abs value ;sub always sets flag so go & report division by 0 if necessary beq divide_by_zero ;get abs value of r1 by xoring with 0xffffffff and adding 1 if negative asr r0, r1, #31 ; get 0 or -1 in r3 depending on sign of r1 eor r1, r0 ; eor with -1 (0 ffffffff) if negative sub r1, r0 ; and add 1 (sub -1) to get abs value ;save signs (0 or -1 in r0 & r2) for later use in determining ; sign of quotient & remainder. push {r0, r2} ;justification, shift 1 bit at a time until divisor (r0 value) ; is just <= than dividend (r1 value). to do this shift dividend ; right by 1 and stop as soon as shifted value becomes >. lsr r0, r1, #1 mov r2, r3 b %ft0 just_l lsl r2, #1 0 cmp r2, r0 bls just_l mov r0, #0 ; set accumulat or to 0 b %ft0 ; branch into division loop div_l lsr r2, #1 0 cmp r1, r2 ; test subtract bcc %ft0 sub r1, r2 ; if successful do a real subtract 0 adc r0, r0 ; shift result and add 1 if subtract succeeded cmp r2, r3 ; terminate when r2 == r3 (ie we hav e just bne div_l ; tested subtracting the 'ones' value).
thumb instruction set S3C2400X01 risc microprocessor 4 - 42 now fix up the signs of the quotient (r0) and remainder (r1) pop {r2, r3} ; get dividend/divisor signs back eor r3, r2 ; result sign eor r0, r3 ; negate if result sign = - 1 sub r0, r3 eor r1, r2 ; negate remainder if dividend sign = - 1 sub r1, r2 mov pc, lr arm code signed_divide ; effectively zero a4 as top bit will be shifted out later ands a4, a1, #&80000000 rsbmi a1, a1, #0 eors ip, a4, a2, asr #32 ;ip bit 31 = sign of result ;ip bit 30 = sign of a2 rsbcs a2, a2, #0 ;central part is identical code to udiv (without mov a4, #0 which comes for free as part of signed entry sequence) movs a3, a1 beq divide_by_zero just_l ; justification stage shifts 1 bit at a t ime cmp a3, a2, lsr #1 movls a3, a3, lsl #1 ; nb: lsl #1 is always ok if ls succeeds blo s_loop div_l cmp a2, a3 adc a4, a4, a4 subcs a2, a2, a3 teq a3, a1 movne a3, a3, lsr #1 bne s_loop2 mov a1, a4 m ovs ip, ip, asl #1 rsbcs a1, a1, #0 rsbmi a2, a2, #0 mov pc, lr
S3C2400X01 risc microprocessor thumb instruction set 4 - 43 division by a constant division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. here is an example of a divide by 10 routine based on the algorithm in the arm cookbook in both thumb and arm code. thumb code udiv10 ; take argument in a1 returns quotient in a1, ; remainder in a2 mov a2, a1 lsr a3, a1, #2 sub a1, a3 lsr a3, a1, #4 add a1, a3 lsr a 3, a1, #8 add a1, a3 lsr a3, a1, #16 add a1, a3 lsr a1, #3 asl a3, a1, #2 add a3, a1 asl a3, #1 sub a2, a3 cmp a2, #10 blt %ft0 add a1, #1 sub a2, #10 0 mov pc, lr arm code udiv10 ; take argument in a1 returns quotient in a1, ; remainder in a2 sub a2, a1, #10 sub a1, a1, a1, lsr #2 add a1, a1, a1, lsr #4 add a1, a1, a1, lsr #8 add a1, a1, a1, lsr #16 mov a1, a1, lsr #3 add a3, a1, a1, asl #2 subs a2, a2, a3, asl #1 addpl a1, a1, #1 addmi a2, a2, #10 mov pc, lr
s3c2400 risc microprocessor memory controller 5- 1 5 memory controller overview the s3c2400 memory controller provides the necessary memory control signals for external memory access. s3c2400 has the following features; ? little/big endian (selectable by a s/w) ? address space: 32mbytes per each bank (tot al 256mb: 8 banks) ? programmable access size (8/16/32-bit) for all banks ? total 8 memory banks 6 memory banks for rom, sram etc. 2 memory banks for rom, sram, edo/sdram etc . ? 7 fixed memory bank start address and programmble bank size ? 1 flexible memo ry bank start address and programmable bank size ? programmable access cycles for all memory banks ? external wait to extend the bus cycles ? supports self-refresh mode in dram/sdram for power-down ? supports asymmetrically or symmetrically addressable dra m
memory controller s 3c2400 risc microprocessor 5- 2 srom/dram/sdram (ngcs7) srom (ngcs5) srom/dram/sdram (ngcs6) srom (ngcs4) srom (ngcs3) srom (ngcs2) srom (ngcs1) 32mb 32mb 32mb 32mb 32mb 2mb/4mb/8mb/ 16mb/32mb 2mb/4mb/8mb/ 16mb/32mb 256mb sa[27:0] accessable region note: srom means rom or sram type memory refer to table 4-1 0x0c00_0000 0x0a00_0000 0x0800_0000 0x0600_0000 0x0400_0000 0x0200_0000 0x1000_0000 0x0e00_0000 srom (ngcs0) 32mb 0x0000_0000 special function register (apb) 0x15ff_ffff 0x1500_0000 special function register (ahb) 0x1400_0000 figure 5-1. s3c2400 memory map after reset table 5-1. bank 6/7 address address 2mb 4mb 8mb 16mb 32mb bank 6 start address 0xc00_0000 0xc00_0000 0xc00_0000 0xc00_0000 0xc00_0000 end address 0xc1f_ffff 0xc3f_ffff 0xc7f_ffff 0xcff_ffff 0xdff_ffff bank 7 start address 0xc20_0000 0xc40_0000 0xc80_0000 0xd00_0000 0xe00_0000 end address 0xc3f_ffff 0xc7f_ffff 0xcff_ffff 0xdff_ffff 0xfff_ffff note: bank 6 and 7 must have the same memory size.
s3c2400 risc microprocessor memory controller 5- 3 function description bank0 bus width the data bus width of bank0 (ngcs0) should be configured as one of 8-bit,16-bit and 32-bit. because the bank0 is the booting rom bank(map to 0x0000_0000), the bus width of bank0 should be determined before the first rom access, which will be determined by the logic level of om[1:0] at reset. om1 (operating mode 1) om0 (operating mode 0) booting rom data width 0 0 8-bit 0 1 16-bit 1 0 32-bit 1 1 test mode programming memory controller all thirteen memory control registers have to be written using the stmia instruction as shown in the following example; ;set memory control registers ldr r0,=smrdata ldr r1,=bwscon ; bwscon address add r2, r0, #52 ; end address of smrdata 0 ldr r3, [r0], #4 str r3, [r1], #4 cmp r2, r0 bne %b0 smrdata data dcd 0x22221210 ; bwscon dcd 0x00000600 ; gcs0 dcd 0x00000700 ; gcs1 dcd 0x00000700 ; gcs2 dcd 0x00000700 ; gcs3 dcd 0x 00000700 ; gcs4 dcd 0x00000700 ; gcs5 dcd 0x0001002a ; gcs6, edo dram(trcd=3, tcas=2, tcp=1, can=10bit) dcd 0x0001002a ; gcs7, edo dram dcd 0x00960000 + 953 ; refresh(refen=1, trefmd=0, trp=3, tr c=5, tchr=3) dcd 0x0 ; bank size, 32mb/32mb dcd 0x20 ; mrsr 6(cl=2) dcd 0x20 ; mrsr 7(cl=2) memory (srom/dram/sdram) address pin connections memory address pin s3c2400 address @ 8-bit data bus s3c2400 address @ 16-bit data bus s3c2400 address @ 32-bit data bus a0 a0 a1 a2 a1 a1 a2 a3
memory controller s 3c2400 risc microprocessor 5- 4 sdram bank address pin connection table 5-2. sdram bank address configuration bank size bus width base component memory configuration bank address 2mbyte 8 16mbit (1m 8 2b) 1 a20 16 (512k 16 2b) 1 4mb 8 16mb (2m 4 2b) 2 a21 16 (1m 8 2b) 2 32 (512k 16 2b) 2 8mb 16 16mb (2m 4 2b) 4 a22 32 (1m 8 2b) 4 8 64mb (4m 8 2b) 1 8 (2m 8 4b) 1 a[22:21] 16 (2m 16 2b) 1 a22 16 (1m 16 4b) 1 a[22:21] 32 (512k 32 4b) 1 16mb 32 16mb (2m 4 2b) 8 a23 8 64mb (8m 4 2b) 2 8 (4m 4 4b) 2 a[23:22] 16 (4m 8 2b) 2 a23 16 (2m 8 4b) 2 a[23:22] 32 (2m 16 2b) 2 a23 32 (1m 16 4b) 2 a[23:22] 8 128mb (4m 8 4b) 1 16 (2m 16 4b) 1 32mb 16 64mb (8m 4 x 2b) 4 a24 16 (4m 4 x 4b) 4 a[24:23] 32 (4m 8 2b) 4 a24 32 (2m 8 4b) 4 a[24:23] 16 128mb (4m 8 4b) 2 32 (2m 16 4b) 2 8 256mb (8m 8 4b) 1 16 (4m 16 4b) 1
s3c2400 risc microprocessor memory controller 5- 5 n wait pin operation if the wait corresponding each memory bank is enabled, the noe duration should be prolonged by the external nwait pin while the memory bank is active. nwait is checked from tacc-1. noe will be deasserted at the next clock after sampling that nwait is high. nwe signal have same relation with noe as 5-14.. trc tacs tcos tacc=3 hclk addr ngcs noe nwait data(r) delayed figure 5-2. s3c2400 external nwait timing diagram (tacc=3)
memory controller s 3c2400 risc microprocessor 5- 6 nxbreq/ nxback pin operation if nxbreq is asserted, s3c2400 will respond by lowering nxback. if nxback=l, the address/data bus and memory control signals are in hi-z state as shown in table 1-1. when nxbreq is de-asserted, the nxback will be de- asserted. hclk a[24:0] d[31:0] ngcs noe nwe nwbe nxbreq ~ ~ ~ ~ nxack ~ ~ ~ ~ figure 5-3. s3c2400 nxbreq/ nxback timing diagram
s3c2400 risc microprocessor memory controller 5- 7 rom memory interface example a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d0 d1 d2 d3 d4 d5 d6 d7 nwe noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce figure 5-4. memory interface with 8bit rom a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d0 d1 d2 d3 d4 d5 d6 d7 nwbe0 noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d8 d9 d10 d11 d12 d13 d14 d15 nwbe1 noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce figure 5-5. memory interface with 8bit rom x 2 note: when addr[n] out of s3c2400 passed through the damping resistances, addr[n] are converted into a[n].
memory controller s 3c2400 risc microprocessor 5- 8 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 d0 d1 d2 d3 d4 d5 d6 d7 nwbe0 noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 d8 d9 d10 d11 d12 d13 d14 d15 nwbe1 noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 d16 d17 d18 d19 d20 d21 d22 d23 nwbe2 noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 d24 d25 d26 d27 d28 d29 d30 d31 nwbe3 noe ngcsn a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 nwe noe nce figure 5-6. memory interface with 8bit rom x 4 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nwe noe nce nwe noe ngcsn figure 5-7. memory interface with 16bit rom
s3c2400 risc microprocessor memory controller 5- 9 sram memory interface example a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nwe noe ncs nub nlb nwe noe ngcsn nbe1 nbe0 figure 5-8. memory interface with 16bit sram a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nwe noe ncs nub nlb nwe noe ngcsn nbe1 nbe0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nwe noe ncs nub nlb nwe noe ngcsn nbe2 nbe3 figure 5-9. memory interface with 16bit sram x 2
memory controller s 3c2400 risc microprocessor 5- 10 dram memory interface example a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nras nlcas nucas nwe noe nras0 ncas0 ncas1 nwe figure 5-10. memory interface with 16bit dram a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nras nlcas nucas nwe noe nras0 ncas0 ncas1 nwe a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nras nlcas nucas nwe noe nras0 ncas2 ncas3 nwe figure 5-11. memory interface with 16bit dram x 2
s3c2400 risc microprocessor memory controller 5- 11 sdram memory interface example a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nscs nsras nscas nwe nscs0 nsras nscas nwe a21 a22 dqm0 dqm1 scke sclk ba0 ba1 ldqm udqm scke sclk figure 5-12. memory interface with 16bit sdram (4mx16, 4bank) a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nscs nsras nscas nwe nscs0 nsras nscas nwe a22 a23 dqm0 dqm1 scke sclk ba0 ba1 ldqm udqm scke sclk a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 nscs nsras nscas nwe nscs0 nsras nscas nwe a22 a23 dqm2 dqm3 scke sclk ba0 ba1 ldqm udqm scke sclk figure 5-13. memory interface with 16bit sdram (4mx16 * 2ea, 4bank) note: please refer to table 5-2 the bank address configurations of sdram.
memory controller s 3c2400 risc microprocessor 5- 12 programmable access cycle tcoh tcos tacs hclk a[24:0] ngcs noe nwe nwbe d[31:0](r) d[31:0] (w) tacc tacp tcah tacs = 1 cycle tcos = 1 cycle tacc = 3 cycles tacp = 2 cycles tcoh = 1 cycle tcah = 2 cycles figure 5-14. s3c2400 x ngcs timing diagram
s3c2400 risc microprocessor memory controller 5- 13 tcas trcd trp hclk addr nras ncas nwe/noe tcas tcp column addr. column addr. row addr. data (r) @edo d[31:0] (w) trp = 1 cycle trcd = 2 cycle tcas = 2 cycle tcp = 2 cycle figure 5-15. s3c2400 dram timing diagram tcsr tchr mclk nras ncas ~ ~ ~ ~ tcsr = 1 cycle tchr = 3 cycle figure 5-16. s3c2400 dram refresh timing diagram
memory controller s 3c2400 risc microprocessor 5- 14 mclk scke nscs nscas addr a10/ap ra nsras ba data (cl2) data (cl3) nwe dqm trp trcd ra ca da da ba ba cb cc cd ce db dc dd de db dc dd de ba ba ba ba ba bank precharge row active write read (cl = 2, cl = 3, bl = 1) trp = 2 cycle tcas = 2 cycle trcd = 2 cycle tcp = 2 cycle figure 5-17. s3c2400 sdram timing diagram
s3c2400 risc microprocessor memory controller 5- 15 bus width & wait control register (bwscon) register address r/w description reset value bwscon 0x14000000 r/w bus width & wait status control register 0x000000 bwscon bit description initial state st7 [31] this bit determines sram for using ub/lb for bank 7 0 = not using ub/lb (pin[154:151] is dedicated nwbe[3:0]) 1 = using ub/lb (pin[154:151] is dedicated nbe[3:0]) 0 ws7 [30] this bit determines wait status for bank 7 0 = wait disable 1 = wait enable 0 dw7 [29:28] these two bits determine data bus width for bank 7 00 = 8-bit 01 = 16-bit, 10 = 32-bit 0 st6 [27] this bit determines sram for using ub/lb for bank 6 0 = not using ub/lb (pin[154:151] is dedicated nwbe[3:0]) 1 = using ub/lb (pin[154:151] is dedicated nbe[3:0]) 0 ws6 [26] this bit determines wait status for bank 6 0 = wait disable, 1 = wait enable 0 dw6 [25:24] these two bits determine data bus width for bank 6 00 = 8-bit 01 = 16-bit, 10 = 32-bit 0 st5 [23] this bit determines sram for using ub/lb for bank 5 0 = not using ub/lb (pin[154:151] is dedicated nwbe[3:0]) 1 = using ub/lb (pin[154:151] is dedicated nbe[3:0]) 0 ws5 [22] this bit determines wait status for bank 5 0 = wait disable, 1 = wait enable 0 dw5 [21:20] these two bits determine data bus width for bank 5 00 = 8-bit 01 = 16-bit, 10 = 32-bit 0 st4 [19] this bit determines sram for using ub/lb for bank 4 0 = not using ub/lb (pin[154:151] is dedicated nwbe[3:0]) 1 = using ub/lb (pin[154:151] is dedicated nbe[3:0]) 0 ws4 [18] this bit determines wait status for bank 4 0 = wait disable 1 = wait enable 0 dw4 [17:16] these two bits determine data bus width for bank 4 00 = 8-bit 01 = 16-bit, 10 = 32-bit 0 st3 [15] this bit determines sram for using ub/lb for bank 3 0 = not using ub/lb (pin[154:151] is dedicated nwbe[3:0]) 1 = using ub/lb (pin[154:151] is dedicated nbe[3:0]) 0 ws3 [14] this bit determines wait status for bank 3 0 = wait disable 1 = wait enable 0 dw3 [13:12] these two bits determine data bus width for bank 3 00 = 8-bit 01 = 16-bit, 10 = 32-bit 0 st2 [11] this bit determines sram for using ub/lb for bank 2 0 = not using ub/lb (pin[154:151] is dedicated nwbe[3:0]) 1 = using ub/lb (pin[154:151] is dedicated nbe[3:0]) 0
memory controller s 3c2400 risc microprocessor 5- 16 bus width & wait control register (bwscon) (continued) bwscon bit description initial state ws2 [10] this bit determines wait status for bank 2 0 = wait disable 1 = wait enable 0 dw2 [9:8] these two bits determine data bus width for bank 2 00 = 8-bit 01 = 16-bit, 10 = 32-bit 0 st1 [7] this bit determines sram for using ub/lb for bank 1 0 = not using ub/lb (pin[154:151] is dedicated nwbe[3:0]) 1 = using ub/lb (pin[154:151] is dedicated nbe[3:0]) 0 ws1 [6] this bit determines wait status for bank 1 0 = wait disable, 1 = wait enable 0 dw1 [5:4] these two bits determine data bus width for bank 1 00 = 8-bit 01 = 16-bit, 10 = 32-bit 0 dw0 [2:1] indicates data bus width for bank 0 (read only) 00 = 8-bit 01 = 16-bit, 10 = 32-bit the states are selected by om[1:0] pins - reserved [0] - note : 1. all types of master clock in this memory controller correspond to the bus clock. for example, hclk in dram and sram is same as the bus clock, and sclk in sdram is also the same as the bus clock. in this chapter (memory controller), one clock means one bus clock. 2. nbe[3:0] is the 'and' signal nwbe[3:0] and noe
s3c2400 risc microprocessor memory controller 5- 17 bank control register ( bankconn: ngcs0-ngcs5) register address r/w description reset value bankcon0 0x14000004 r/w bank 0 control register 0x0700 bankcon1 0x14000008 r/w bank 1 control register 0x0700 bankcon2 0x1400000c r/w bank 2 control register 0x0700 bankcon3 0x14000010 r/w bank 3 control register 0x0700 bankcon4 0x14000014 r/w bank 4 control register 0x0700 bankcon5 0x14000018 r/w bank 5 control register 0x0700 bankconn bit description initial state tacs [14:13] address set-up before ngcsn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tcos [12:11] chip selection set-up noe 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tacc [10:8] access cycle 000 = 1 clock 001 = 2 clocks 010 = 3 clocks 011 = 4 clocks 100 = 6 clocks 101 = 8 clocks 110 = 10 clocks 111 = 14 clocks note: when nwait signal is used, tacc 3 4 clocks. 111 toch [7:6] chip selection hold on noe 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 000 tcah [5:4] address holding time after ngcsn 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tacp [3:2] page mode access cycle @ page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks 00 pmc [1:0] page mode configuration 00 = normal (1 data) 01 = 4 data 10 = 8 data 11 = 16 data 00
memory controller s 3c2400 risc microprocessor 5- 18 bank control register ( bankcon n : n gcs6- n gcs7) register address r/w description reset value bankcon6 0x1400001c r/w bank 6 control register 0x18008 bankcon7 0x14000020 r/w bank 7 control register 0x18008 bankconn bit description initial state mt [16:15] these two bits determine the memory type for bank6 and bank7 00 = rom or sram 01 = reserved(don't use) 10 = edo dram 11 = sync. dram 11 memory type = rom or sram [mt=00] (15-bit) tacs [14:13] address set-up before ngcs 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tcos [12:11] chip selection set-up noe 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tacc [10:8] access cycle 000 = 1 clock 001 = 2 clocks 010 = 3 clocks 011 = 4 clocks 100 = 6 clocks 101 = 8 clocks 110 = 10 clocks 111 = 14 clocks 111 toch [7:6] chip selection hold on noe 00 = 0 clock 01 = 1 clock 10 = 2 clocks 11 = 4 clocks 00 tcah [5:4] address hold time on ngcsn 00 = 0 clock 01 = 1clock 10 = 2 clocks 11 = 4 clocks 00 tacp [3:2] page mode access cycle @ page mode 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = 6 clocks 00 pmc [1:0] page mode configuration 00 = normal (1 data) 01 = 4 consecutive accesses 10 = 8 consecutive accesses 11 = 16 consecutive accesses 00 memory type = edo dram [mt=10] (6-bit) trcd [5:4] ras to cas delay 00 = 1 clock 01 = 2 clocks 10 = 3 clocks 11 = 4 clocks 00 tcas [3] cas pulse width 0 = 1 clock 1 = 2 clocks 0 tcp [2] cas pre-charge 0 = 1 clock 1 = 2 clocks 0 can [1:0] column address number 00 = 8-bit 01 = 9-bit 10 = 10-bit 11 = 11-bit 00
s3c2400 risc microprocessor memory controller 5- 19 bank control register ( bankcon n : n gcs6- n gcs7) ( continued ) memory type = sdram [mt=11] (4-bit) trcd [3:2] ras to cas delay 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 10 scan [1:0] column address number 00 = 8-bit 01 = 9-bit 10= 10-bit 00 supported bank 6/7 memory configuration bank support not support bank7 srom srom dram dram sdram sdram sdram dram bank6 dram sdram srom dram srom sdram dram sdram note: srom means rom or sram type memory refresh control register register address r/w description reset value refresh 0x14000024 r/w dram/sdram refresh control register 0xac0000 refresh bit description initial state refen [23] dram/sdram refresh enable 0 = disable 1 = enable(self or cbr/auto refresh) 1 trefmd [22] dram/sdram refresh mode 0 = cbr/auto refresh 1 = self refresh in self-refresh time, the dram/sdram control signals are driven to the appropriate level. 0 trp [21:20] dram/sdram ras pre-charge time dram: 00 = 1.5 clocks 01 = 2.5 clocks 10 = 3.5 clocks 11 = 4.5 clocks sdram: 00 = 2 clocks 01 = 3 clocks 10 = 4 clocks 11 = not support 10 trc [19:18] sdram rc minimum time 00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocks 11 tchr [17:16] cas hold time(dram) 00 = 1 clock 01 = 2 clocks 10 = 3 clocks 11 = 4 clocks 00 reserved [15:11] not use 0000 refresh counter [10:0] dram/sdram refresh count value. please, refer to chap. 6 dram refresh controller bus priority section. refresh period = (2 11 -refresh_count+1)/hclk ex) if refresh period is 15.6 us and hclk is 60 mhz, the refresh count is as follows; refresh count = 2 11 + 1 - 60x15.6 = 1113 0
memory controller s 3c2400 risc microprocessor 5- 20
s3c2400 risc microprocessor memory controller 5- 21 banksize register register address r/w description reset value banksize 0x14000028 r/w flexible bank size register 0x0 banksize bit description initial state sclken [4] sclk is enabled only during sdram access cycle for reducing power consumption. when sdram isn't be accessed, sclk is 'l' level. 0 = sclk is always active 1 = sclk is active only during the access (recommended) 0 reserved [3] not used 0 bk76map [2:0] bank6/7 memory map 000 = 32m/32m 100 = 2m/2m 101 = 4m/4m 110 = 8m/8m 111 = 16m/16m 000
memory controller s 3c2400 risc microprocessor 5- 22 sdram mode register set register (mrsr) register address r/w description reset value mrsrb6 0x1400002c r/w mode register set register bank6 xxx mrsrb7 0x14000030 r/w mode register set register bank7 xxx mrsr bit description initial state reserved [11:10] not use ? wbl [9] write burst length 0 = burst(fixed) 1 = reserved x tm [8:7] test mode 00 = mode register set(fixed) 01, 10, 11 = reserved xx cl [6:4] cas latency 000 = 1 clock, 010 = 2 clocks, 011=3 clocks the others : reserved xxx bt [3] burst type 0 = sequential(fixed) 1 = reserved x bl [2:0] burst length 000 = 1(fixed) the others = reserved xxx note: mrsr register must not be reconfigured while the code is running on sdram. important notes 1. all 13 memory control registers have to be written using the stm instruction (not stmia instruction). 2. in stop mode/sl_idle mode, dram/sdram has to enter the dram/sdram self-refresh mode.
s3c2400 risc microprocessor memory controller 5- 23 notes
s3c2400 risc microprocessor clock & power management 6- 1 6 clock & power management overview the clock & power management unit consists of 3 parts, clock control, usb control, and power control. the clock control logic in s3c2400 can generate the required clock signals, fclk for cpu, hclk for the ahb bus peripherals, and pclk for the apb bus peripherals. there are two pll in s3c2400. one is for fclk,hclk, and pclk, the other is dedicated for usb block (48mhz). the clock control logic can make slow clock without pll and connect/disconnect the clock to each peripheral block by s/w, which will reduce the power consumption. in the power control logic, s3c2400 has various power management schemes to keep optimal power consumption for a given task. the power management in s3c2400 consists of five modes: normal mode, slow mode, idle mode, stop mode and sl_idle mode for the self-refresh mode lcd. normal mode is used to supply clocks to cpu as well as all peripherals in s3c2400. in this case, the power consumption will be maximized when all peripherals are turned on. the user can control the operation of peripherals by s/w. for example, if a timer is not needed, the user can disconnect the clock to the timer to reduce power. slow mode is non-pll mode. unlike the normal mode, the slow mode uses an external clock (xtipll or extclk) directly as fclk in s3c2400 without pll. in this case, the power consumption depends on the frequency of the external clock only. the power consumption due to pll itself is excluded. idle mode disconnects the clock (fclk) only to cpu core while it supplies the clock to all peripherals. by using idle mode, power consumption due to cpu core can be reduced. any interrupt request to cpu can wake-up from idle mode. stop mode freezes all clocks to the cpu as well as peripherals by disabling plls. the power consumption is only due to the leakage current in s3c2400, which is ua unit. the wake-up from stop mode can be done by activating external interrupt pins or rtc alarm. sl_idle mode causes the lcd controller to work. in this case, the clock to cpu and all peripherals except lcd controller should be stopped, therefore, the power consumption in the sl_idle mode is less than that in the idle mode.
clock & power management s3c2400 risc microprocessor 6- 2 function description clock architecture figure 6-1 shows a block diagram of the clock architecture. the main clock source comes from an external crystal(xtipll) or external clock(extclk). the clock generator consists of an oscillator block(oscillation amplifier) which is connected to an external crystal, and also has two plls (phase-locked-loop) which generate the high frequency clock required in s3c2400. clock source selection table 6-1 shows the relationship between the combination of mode control pins (om3 and om2) and the selection of source clock for s3c2400. the om[3:2] status is latched internally by referring the om3 and om2 pins at the rising edge of nreset. table 6-1. clock source selection at boot-up mode om[3:2] mpll state upll state main clock source usb clock source 00 on (1) on (1) crystal crystal 01 on (1) on (1) crystal extclk 10 on (1) on (1) extclk crystal 11 on (1) on (1) extclk extclk notes: 1. although the m(u)pll starts just after a reset, the m(u)pll output(mpll,upll) isn't used as the system clock until the s/w writes valid settings to the m(u)pllcon register. before this vali d setting, the clock from external crystal or extclk source will be used as the system clock directly. even if the user wants to maintain the default value of mpllcon register, the user should write the same value into m(u)pllcon register. 2. om[3:2] is used to determine test mode when om[1:0] is 11.
s3c2400 risc microprocessor clock & power management 6- 3 osc mpll upll clkcntl fclk hdivn pdivn mpll control signal upll powcntl f h p usbcntl test mode om[1:0] bus controller memory controller arbitration dma 4ch extmaster usb host i/f tic wdt i 2 s mmc adc uart(0,1) pwm i 2 c gpio rtc spi(0,1) usb device arm920t interrupt controller lcd controller h_lcd p_mmc p_gpio p_adc p_rtc p_uart p_spi p_i 2 c p_i 2 c p_pwm p_usb h_usb fclk pclk hclk uclk power management block mpll clk upll clk hclk pclk fclk clkout xtipll xtopll extclk p[5:0] m[7:0] s[1:0] figure 6-1. clock generator block diagram
clock & power management s3c2400 risc microprocessor 6- 4 pll (phase-locked-loop) the mpll within the clock generator is the circuit which synchronizes an output signal with a reference input signal in frequency and phase. in this application, it includes the following basic blocks (figure 6-2 shows the clock generator block diagram); the vco(voltage controlled oscillator) to generate the output frequency proportional to input dc voltage, the divider p to divide the input frequency(fin) by p, the divider m to divide the vco output frequency by m which is input to pfd(phase frequency detector), the divider s to divide the vco output frequency by s which is mpll(the output frequency from mpll block), the phase difference detector, charge pump, and loop filter. the output clock frequency mpll is related to the reference input clock frequency fin by the following equation: mpll = (m * fin) / (p * 2 s ) m = m (the value for divider m)+ 8, p = p(the value for divider p) + 2 the upll within the clock generator is same as the mpll in every aspect. the following sections describe the operation of the pll, that includes the phase difference detector, charge pump, vco (voltage controlled oscillator), and loop filter. phase difference detector(pfd) the pfd monitors the phase difference between the fref (the reference frequency as shown in fig. 6-2) and fvco, and generates a control signal(tracking signal) when it detects a difference. charge pump(pump) the charge pump converts the pfd control signal into a proportional charge in voltage across the external filter that drives the vco. loop filter the control signal that the pfd generates for the charge pump, may generate large excursions(ripples) each time the fvco is compared to the fref. to avoid overloading the vco, a low pass filter samples and filters the high- frequency components out of the control signal. the filter is typically a single-pole rc filter consisting of a resistor and capacitor. a recommended capacitance in the external loop filter(capacitance as shown in figure 6-2) is 5 pf or above. voltage controlled oscillator (vco) the output voltage from the loop filter drives the vco, which causes its oscillation frequency to increase or decrease linearly as a function of variations in average voltage. when the fvco matches fref in terms of frequency as well as phase, the pfd stops sending a control signal to the charge pump, which stabilizes the input voltage to the loop filter in turn. the vco frequency then remains constant, and the pll remains locked onto the system clock. usual conditions for pll & clock generator the following conditions are generally used. loop filter capacitance for upll/mpll 5 pf external x-tal frequency 10 - 20 mhz (note) external capacitance used for x-tal 15 - 22 pf note: value could be changed.
s3c2400 risc microprocessor clock & power management 6- 5 divider p loop filter fin m[7:0] s[1:0] pfd divider m p[5:0] f vco pump vco divider s f ref mpll,upll r c internal m/upll cap figure 6-2. pll (phase-locked loop) block diagram extclk xtipll xtopll extclk xtipll xtopll external osc a) x-tal oscillation(om[3:2]=00) b) external clock source(om[3:2]=11) v dd v dd figure 6-3. main oscillator circuit examples
clock & power management s3c2400 risc microprocessor 6- 6 clock control logic the clock control logic determines the clock source to be used, i.e., the pll clock(mpll) or the direct external clock(xtipll or extclk). when pll is configured to a new frequency value, the clock control logic disables the fclk until the pll output is stabilized using the pll locking time. the clock control logic is also activated at power-on reset and wake-up from power-down mode. pll lock time the lock time is the minimum time required for pll output stabilization. the lock time should be a minimum of 150us. after reset and wake-up from stop and sl_idle mode, respectively, the lock-time is inserted automatically by the internal logic with lock time count register. the automatically inserted lock time is calculated as follows; t_lock(the pll lock time by h/w logic) = (1/ fin) x n, (n = m_ltime,u_ltime value) power-on reset(xtipll) figure 6-4 shows the clock behavior during the power-on reset sequence. the crystal oscillator begins oscillation within several milliseconds. when nreset is released after the stabilization of osc(xtipll) clock, the pll starts to operate according to the default pll configuration. however pll is commonly known to be unstable after power-on reset, so fin fed directly to fclk instead of the mpll(pll output) before the s/w newly configures the pllcon. even if the user wants to use the default value of pllcon register after reset, user should write the same value into pllcon register by s/w. the pll begins the lockup sequence again toward the new frequency only after the s/w configures the pll with a new frequency. fclk can be configured to be pll output (mpll) immediately after lock time. the logic operates by xtipll nreset osc (xtipll) vco output power clock disable lock time pll is configured by s/w first time. vco is adapted to new clock frequency. fclk fclk is new frequency figure 6-4. power-on reset sequence (when the external clock source is a crystal oscillator.)
s3c2400 risc microprocessor clock & power management 6- 7 change pll settings in normal operation mode during the operation of s3c2400 in normal mode, if the user wants to change the frequency by writing the pms value, the pll lock time is automatically inserted. during the lock time, the clock is not supplied to the internal blocks in s3c2400. the timing diagram is as follow. mpll pms setting pll lock-time fclk it changes to new pll clock after lock time automatically figure 6-5. timing diagram of changing fclk note: changing pms value can cause problem in lcd display. because changed pms value means changed clkval of lcd control register. in this case, the user has to use slow mode like the below.
clock & power management s3c2400 risc microprocessor 6- 8 clkslow register slow_bit clkslow register mpll_off hclk lcd frame lcdcon1 register clkval lcdcon5 register slowclksync (n-1)th frame clkval @slow(b clk) clkval@normal(c clk) n-th frame power mode normal(a clk) (n+1)th frame slow(b clk) normal(c clk) lock time b clk a clk c clk pms setting figure 6-6. timing diagram of changing pms without the interference of lcd display
s3c2400 risc microprocessor clock & power management 6- 9 fclk, hclk, pclk fclk is used by arm920t. hclk is used for ahb bus which is used by arm920t, the memory controller, the interrupt controller, lcd controller, the dma and the usb host block. pclk is used for apb bus which is used by the peripherals such as wdt,iis,i2c,pwm timer, mmc interface, adc, uart, gpio, rtc and spi. s3c2400 supports selection of dividing ratio between fclk, hlck and pclk. this ratio is determined by hdivn and pdivn of clkdivn control register. hdivn pdivn fclk hclk pclk divide ratio 0 0 fclk fclk fclk 1 : 1 : 1(default) 0 1 fclk fclk fclk / 2 1 : 1 : 2 1 0 fclk fclk / 2 fclk / 2 1 : 2 : 2 1 1 fclk fclk / 2 fclk / 4 1 : 2 : 4 when pms value is set, clkdivn register should be set after pms setting. these values of clkdivn are valid after pll lock-time. which one of values is also available after reset and changing power management mode. in other case, the setting value of clkdivn register is valid after 1.5 hclk. but 1hclk can be validated the value of clkdivn register changed from default(1:1:1) to other divide ratio(1:1:2, 1:2:2 and 1:2:4) 1 hclk clkdivn fclk hclk pclk 1.5 hclk 1.5 hclk 0x00000000 0x00000001(1:1:2) 0x00000003 (1:2:4) 0x00000000 (1:1:1) figure 6-7. example that changes clkdivn register value note: clkdivn should be set carefully not to exceed the limit of hclk & pclk.
clock & power management s3c2400 risc microprocessor 6- 10 usb clock control usb host interface and usb device interface needs 48mhz clock. in s3c2400, the usb dedicated pll(upll) generates 48mhz for usb. uclk doesn't fed until the pll(upll) is configured. usb pll(upll) will be turned off during sl_idle mode or stop mode automatically. also, usb pll(upll) will be turned on after exiting sl_idle mode or stop mode if uclk_on bit is enabled in clkslow register. condition uclk state upll state after reset xti pll or extclk on after configuring upll l: during pll lock time 48 mhz: after pll lock time on upll is turned off by clkslow register xti pll or extclk off upll is turned on by clkslow register 48 mhz on power management the power management block controls the system clocks by software for the reduction of power consumption in s3c2400. these schemes are related to pll, clock control logic(fclk,hclk,pclk) and wake-up signal. the figure 6-8 depicts the clock distribution of s3c2400. s3c2400 has five power-down modes. the following section describes each power managing mode. the transition between the modes is not allowed freely. for available transitions among the modes, please refer to figure 6-9.
s3c2400 risc microprocessor clock & power management 6- 11 module a module b module a module a module a module a module a module a module b module b module b module b module b module b 66 mhz gclk sclk cpuw rtca pwrack pwrmanoff wku mclk pmsset wakeup p m s powerdown powerslow figure 6-8. the clock distribution block diagram
clock & power management s3c2400 risc microprocessor 6- 12 idle_bit=1 & sl_idle_bit=1 set idle_bit=0 & stop_bit=0 sl_idle idle stop normal (slow_bit=0) slow (slow_bit=1) eint ,rtc alarm idle_bit=1 interrupts, eint, rtc alarm stop_bit=1 eint, rtc alarm (pll is turned on automatically) reset figure 6-9. power management state machine table 6-2. functional block clock state in each power mode mode arm920t ahb modules (1) , wdt lcd apb modules (2) , usb host uclk normal o o sel sel sel idle x o sel sel sel sl_idle x x o x sel stop x x x x (3) x slow o o sel sel sel notes: 1. usb host and rtc are excluded. 2. wdt is excluded. 3. rtc in terface is turned off in stop mode but rtc timer is always turned on. 4. sel: selectable, o: turned on, x: turned off
s3c2400 risc microprocessor clock & power management 6- 13
clock & power management s3c2400 risc microprocessor 6- 14 normal mode in normal mode, all peripherals and the basic blocks(power management block, cpu core, bus controller, memory controller, interrupt controller, dma, and external master) may operate fully. but, the clock to each peripheral, except the basic blocks, can be stopped selectively by s/w to reduce power consumption. idle mode in idle mode, the clock to cpu core is stopped except bus controller, memory controller, interrupt controller, and power management block. to exit idle mode, eint, or rtc alarm interrupt, or the other interrupts should be activated. (if users are willing to use eint, gpio block has to be turned on before the activation). stop mode in stop mode, all clocks are stopped for minimum power consumption. therefore, the pll and oscillator circuit are also stopped. just after exiting the stop mode, only normal mode is available. in figure 6-9, the user must return from stop mode to normal mode. to exit from stop mode, eint or rtc alarm has to be activated and clkcon register is set properly. ? dram has to be in self-refresh mode during stop mode to retain valid memory data. ? lcd must be stopped before stop mode, because dram can't be accessed when it ? s in self-refresh mode. ? all interrupts should be masked, because dram can't be accessed when it ? s in self-refresh mode. (even though all interrupts are masked, eint can wake-up s3c2400 with the setting of exint register.) ? if mmu is turned on, tlb fill operation should not be allowed after entering stop mode because sdram is entered the self-refresh mode. so, the tlb should be filled in advance. please refer to our reference code. the s3c2400 can exit from stop mode by eint(external interrupts) or rtc alarm. during the wake-up sequences, the crystal oscillator and pll may begin to operate. the lock time is also needed to stabilize fclk. the lock time is inserted automatically and guaranteed by power management logic. during this lock time the clock is not supplied. just after wake-up sequences wake-up interrupt(rtc alarm or external interrupt) is requested.
s3c2400 risc microprocessor clock & power management 6- 15 xtipll or extclk wake-up vco output clock disable fclk several slow clocks (xtipll or extclk) stop mode is initiated. lock time figure 6-10. entering stop mode and exiting stop mode (wake-up)
clock & power management s3c2400 risc microprocessor 6- 16 sl_idle mode (s_lcd mode) in sl_idle mode, the clock to the basic blocks is stopped. only the lcd controller is working to maintain the lcd screen. less power is consumed in the sl_idle mode than in the idle mode. sdram has to be in self-refresh mode during sl_idle mode to retain the valid data in dram. procedure for entering sl_idle mode. 1. mask all interrupts. 2. check the lcd line counter(linecnt) whether or not sufficient time is remained until entering slow mode. lcd frame should not be changed until step 4. 3. set slowclksync bit in lcd control register 4. wait until the lcd line counter reaches the self-refresh line. (the lcdcon5:selfref bit should be enabled at 4n+1th line to enable the lcd self-refresh at 4n+0 th line.) at the moment that the lcd line reaches the lcd self- refresh line, turn on lcdcon5:selfref bit. 5. reconfigure lcdcon1 for slow clock. these new parameter will be effective from next lcd frame. lcdcon2,3,4 can't be changed. 6. wait until the lcd self-refresh command is effective. 7. turn on slow mode. the slow mode will not be effective until the current lcd frame is completed. 8. as tlb fill operation can't be occurred after sdram self-refresh mode is effective. so, fill the tlb in advance like our example code. 9. wait until the line counter reaches 0. 10. while the line counter is 0, sl_idle mode should be enabled by setting clkcon resister. 11. wait while the line counter is 0. 12. the sl_idle mode will be effective just after the current frame is completed. procedure for exiting from sl_idle mode 1. sl_idle mode is woken up by eint or alarm interrupt. just after wake-up, the operating mode is slow mode. 2. change the clkcon as normal mode(actually, slow mode). 3. check the lcd line counter whether sufficient time is remained or not until exiting s low mode. lcd frame should not be changed until step 4. 4. turn on mpll if the mpll is turned off. 5. configure lcd parameters for normal clock. these new parameter will be effective from next lcd frame. 6. wait until the line counter is 0. 7. turn off slow mode. the normal mode will not be effective until the current lcd frame is completed. 8. wait until the current frame is completed. 9. clear slowclksync bit in lcd control register. 10. wait until normal mode is effective by polling the lcd line count er. 11. wait until the lcd line counter reaches the self-refresh line. (the lcdcon5:selfref bit should be disabled at 4n+1th line to disable the lcd self-refresh at 4n+0 th line.) at the moment that the lcd line reaches the lcd self- refresh line, turn off lcdcon5:selfref bit. 12. unmask interrupts. the interrupt(wake-up source) will be generated.
s3c2400 risc microprocessor clock & power management 6- 17 by s/w wake up by s/w clkslow register slow_bit clkslow register mpll_off hclk lcd frame lcdcon1 register clkval lcdcon5 register slowclksync lcdcon5 register selfref set clkcon register to sl_idle mode (n-1)th frame clkval@slow and sl_idle mode clkval@normal mode linecnt==0 (m+1)th frame n-th frame m-th frame power mode normal sl-idle slow normal lock time figure 6-11. entering sl_idle mode and exiting from sl_idle mode (wake-up)
clock & power management s3c2400 risc microprocessor 6- 18 slow mode (non-pll mode) power consumption can be reduced in the slow mode by applying a slow clock and excluding the power consumption from the pll, itself. the fclk is the frequency of divide_by_n of the input clock(xtipll or extclk) without pll. the divider ratio is determined by slow_val in the clkslow control register and clkdivn control register. table 6-3. clkslow and clkdivn register settings for slow clock slow_val fclk hclk pclk uclk 1/1 option (hdivn=0) 1/2 option (hdivn=1) 1/1 option (pdivn=0) 1/2 option (pdivn=1) 0 0 0 extclk or xtipll / 1 extclk or xtipll / 1 extclk or xtipll / 2 hclk hclk / 2 48mhz 0 0 1 extclk or xtipll / 2 extclk or xtipll / 2 extclk or xtipll / 4 hclk hclk / 2 48mhz 0 1 0 extclk or xtipll / 4 extclk or xtipll / 4 extclk or xtipll / 8 hclk hclk / 2 48mhz 0 1 1 extclk or xtipll / 6 extclk or xtipll / 6 extclk or xtipll / 12 hclk hclk / 2 48mhz 1 0 0 extclk or xtipll / 8 extclk or xtipll / 8 extclk or xtipll / 16 hclk hclk / 2 48mhz 1 0 1 extclk or xtipll / 10 extclk or xtipll / 10 extclk or xtipll / 20 hclk hclk / 2 48mhz 1 1 0 extclk or xtipll / 12 extclk or xtipll / 12 extclk or xtipll / 24 hclk hclk / 2 48mhz 1 1 1 extclk or xtipll / 14 extclk or xtipll / 14 extclk or xtipll / 28 hclk hclk / 2 48mhz in slow mode, the pll will be turned off to reduce the pll power consumption. when pll is turned off in slow mode and users change power mode from slow mode to normal mode, the pll needs clock stabilization time(pll lock time). this pll stabilization time is automatically inserted by the internal logic with lock time count register. the pll stability time will take 150us after pll is turn on. during pll lock time, the fclk is slow clock. users can change the frequency by enabling slow mode bit in clkslow register in pll on state. the slow clock is generated during slow mode. the timing diagram is in figure 6-12.
s3c2400 risc microprocessor clock & power management 6- 19 mpll slow mode disable fclk slow mode enable slow_bit divided external clock mpll_off it changes to pll clock after slow mode off figure 6-12. the case that exit_from_slow_mode command is issued in pll on state
clock & power management s3c2400 risc microprocessor 6- 20 if users exit from slow mode to normal mode by disabling the slow_bit in the clkslow register after pll lock time, the frequency is changed just after slow mode is disabled. the timing diagram is in figure 6-13. mpll fclk slow_bit divided osc clock mpll_off s/w lock time slow mode disable pll off pll on slow mode enable it changes to pll clock after slow mode off figure 6-13. the case that exit_from_slow_mode command is issued after lock time is end if users exit from slow mode to normal mode by disabling slow_bit and mpll_off bit simultaneously in clkslow register, the frequency is changed just after the pll lock time. the timing diagram is as follow. mpll fclk slow_bit divided osc clock mpll_off h/w lock time pll off pll on slow mode enable it changes to pll clock after lock time automatically slow mode disable figure 6-14. the case that the exit_from_slow_mode command and the instant pll_on command is issued aimultaneously
s3c2400 risc microprocessor clock & power management 6- 21 wake-up from stop mode when the s3c2400 is woken up from power down mode(stop mode) by an eint or a rtc alarm interrupt, the pll is turned on automatically. but s3c2400 is not in normal mode yet. because the configuration of the clkcon is ignored. so, the user has to set clkcon register. after the wake-up from stop mode, the processor is not in normal mode as explained above. the new value, which reflects the new state, has to be re-written into the clkcon register. eventually, the processor state will be changed from stop mode to normal mode. table 6-4. the status of pll and fclk after wake-up mode before wake-up pll on/off after wake- up fclk after wake-up and before the lock time fclk after the lock time by internal logic stop off ? on no clock normal mode clock sl_idle off slow clock (the pll lock time is issued by s/w) unchanged idle unchanged unchanged unchanged signaling eint for wake-up the s3c2400 can be woken up from sl_idle mode or stop mode only if the following conditions are met. a) level signal(h or l) or edge signal(rising or falling or both) is asserted on eintn input pin. b) eintn pin has to be configured as eint in the gpio control register. it is important to configure the eintn in the gpio control register as an external interrupt pins. for wake-up, we need h/l level or rising/falling edge or both edge signals on eintn pin. just after wake-up the corresponding eintn pin will not be used for wake-up. this means that these pins can be used as external interrupt request pins again. entering idle mode if clkcon[2] is set to 1 to enter the idle mode, s3c2400 will enter into idle mode after some delay(until when the power control logic receives ack signal from the cpu wrapper). pll on/off the pll can only be turned off for power saving in slow mode. if pll is turned off in any other mode, mcu operation is not guaranteed. when the processor is in slow mode and tries to change its state into other state requiring that pll be turned on, then slow_bit should be clear to move to another state after pll stabilization.
clock & power management s3c2400 risc microprocessor 6- 22 pnups register and stop/sl_idle mode in stop mode, the data bus(d[31:0] or d[15:0] ) is hi-z state. but, because of the characteristics of i/o pad, the data bus pull-up resistors have to be turned on to reduce the power consumption in stop/sl_idle mode. d[31:16] pin pull-up resistors can be controlled by gpio control registers. d[15:0] pin pull-up resistors can be controlled by the gpio control register. output port state and stop/sl_idle mode if output is l, the current will be consumed through the internal parasitic resistance; if the output is h, the current will not be consumed. if a port is configured as an output port, the current consumption can be reduced if the output state is h. the output ports are recommended to be in h state to reduce stop mode current consumption. adc power down the adc has an additional power-down bit(stdbm) in adccon. if s3c2400 enters the stop mode, the adc should enter it's own power-down mode.
s3c2400 risc microprocessor clock & power management 6- 23 clock generator & power management special register lock time count register (locktime) register address r/w description reset value locktime 0x14800000 r/w pll lock time count register 0x00ffffff locktime bit description initial state u_ltime [23:12] upll lock time count value for uclk. (u_ltime>150us) 0xfff m_ltime [11:0] mpll lock time count value for fclk,hclk,pclk (m_ltime>150us) 0xfff pll control register (mpllcon, upllcon) mpll = (m * fin) / (p * 2 s ) m = (mdiv + 8), p = (pdiv + 2), s = sdiv example if fin=14.318mhz and fclk=60mhz, the calculated value is as follows; mdiv=59, pdiv=6 and sdiv=1 (this value may be calculated using pllset.exe utility, provided by samsung.) pll value selection guide 1. mpll * 2 s has to be less than 300 mhz. 2. s should be as great as possible. 3. (fin / p) is recommended to be the value between 2mhz - 3mhz. but, you had better choose the value which is close to 2mhz. register address r/w description reset value mpllcon 0x14800004 r/w mpll configuration register 0x0005c080 upllcon 0x14800008 r/w upll configuration register 0x00028080 pllcon bit description initial state mdiv [19:12] main divider control 0x5c/0x28 pdiv [9:4] pre-divider control 0x08/0x08 sdiv [1:0] post divider control 0x0/0x0 caution: when you set mpll&upll values simultaneously, mpll value mpll value first and then upll value should be set.
clock & power management s3c2400 risc microprocessor 6- 24 clock control register (clkcon) register address r/w description reset value clkcon 0x1480000c r/w clock generator control register 0xfff8 clkcon bit description initial state spi [15] controls pclk into spi block 0 = disable, 1 = enable 1 iis [14] controls pclk into iis block 0 = disable, 1 = enable 1 iic [13] controls pclk into iic block 0 = disable, 1 = enable 1 adc [12] controls pclk into adc block 0 = disable, 1 = enable 1 rtc [11] controls pclk into rtc control block. even if this bit is cleared to 0, rtc timer is alive. 0 = disable, 1 = enable 1 gpio [10] controls pclk into gpio block 0 = disable, 1 = enable 1 uart1 [9] controls pclk into uart1 block 0 = disable, 1 = enable 1 uart0 [8] controls pclk into uart0 block 0 = disable, 1 = enable 1 mmc [7] controls pclk into mmc interface block 0 = disable, 1 = enable 1 pwmtimer [6] controls pclk into pwmtimer block 0 = disable, 1 = enable 1 usb device [5] controls pclk into usb device block 0 = disable, 1 = enable 1 usb host [4] controls hclk into usb host block 0 = disable, 1 = enable 1 lcdc [3] controls hclk into lcdc block 0 = disable, 1 = enable 1 idle bit [2] enters idle mode. this bit isn't be cleared automatically. 0 = disable, 1 = transition to idle(sl_idle) mode 0 sl_idle [1] sl_idle mode option. this bit isn't be cleared automatically. 0 = disable, 1 = sl_idle mode. to enter sl_idle mode, clkcon register has to be 0xe. 0 stop bit [0] enters stop mode. this bit isn't be cleared automatically. 0 = disable 1 = transition to stop mode 0
s3c2400 risc microprocessor clock & power management 6- 25 clock slow control register (clkslow) register address r/w description reset value clkslow 0x14800010 r/w slow clock control register 0x00000004 clkslow bit description initial state uclk_on [7] 0 = uclk on (upll is also turned on and the upll lock time is inserted automatically.) 1 = uclk off(upll is also turned off) 0 reserved [6] reserved ? mpll_off [5] 0 = pll is turned on. after pll stabilization time (minimum 150us), slow_bit can be cleared to 0. 1 = pll is turned off. pll is turned off only when slow_bit is 1. 0 slow_bit [4] 0 = fclk = mpll (mpll output) 1 = slow mode fclk = input clock / (2 x slow_val) (slow_val > 0) fclk = input clock (slow_val = 0) input clock = xtipll or extclk 0 slow_val [2:0] the divider value for the slow clock when slow_bit is on. 0x4 clock divider control register (clkdivn) register address r/w description reset value clkdivn 0x14800014 r/w clock divider control register 0x00000000 clkdivn bit description initial state hdivn [1] 0 = hclk has the clock same as the fclk 1 = hclk has the clock same as the fclk/2 0 pdivn [0] 0 = pclk has the clock same as the hclk 1 = pclk has the clock same as the hclk/2 0
s3c2400 risc microprocessor cpu wrapper & bus priorities 7- 1 7 bus priorities overview the bus arbitration logic determines the priorities of bus masters. it supports a combination of rotation priority mode and fixed priority mode. bus priority map in s3c2400, there are eleven bus masters, i.e., dram refresh controller, lcd_dma, dma0, dma1, dma2, dma3, usb_host_dma, ext_bus_master, tic (test interface controller), and arm920t. the priorities among these bus masters after a reset are as follows: 1. dram refresh controller 2. lcd_dma 3. dma0 4. dma1 5. dma2 6. dma3 7. usb host dma 8. external bus master 9. tic 10. arm920t 11. reserved among those bus masters, four dmas operate under the rotation priority, while others run under the fixed priority.
bus priorities s3c2 400 risc microprocessor 7- 2 notes
s3c2400 risc microprocessor dma 8- 1 8 dma overview s3c2400 supports four-channel dma controller that is located between the system bus and the peripheral bus. each channel of dma controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. in other words, each channel can handle the following four cases: 1) both source and destination are in the system bus, 2) source is in the system bus while destination is in the peripheral bus, 3) source is in the peripheral bus while destination is in the system bus, 4) both source and destination are in the peripheral bus. the main advantage of dma is that it can transfer the data without cpu intervention. the operation of dma can be initiated by s/w, the request from internal peripherals or the external request pins.
dma s3c2400 risc m icroprocessor 8- 2 dma request sources each channel of dma controller can select one of dma request source among four dma sources if h/w dma request mode is selected by dcon register. (note that if s/w request mode is selected, this dma request sources have no meaning at all.) the four dma sources for each channel are as follows. table 8- 1 . dma request sources for each channel source0 source1 source2 source3 ch-0 nxdreq0 uart0 mmc timer ch-1 nxdreq1 uart1 i2ssdi spi ch-2 i2ssdo i2ssdi mmc timer ch-3 usb device mmc spi timer here, nxdreq0 and nxdreq1 represent two external sources(external devices), and i2ssdo and i2ssdi represent iis transmitting and receiving, respectively. dma operation the details of dma operation can be explained using three-state fsm(finite state machine) as follows: state-1. as an initial state, it waits for the dma request. if it comes, go to state-2. at this state, dma ack and int req are 0. state-2. in this state, dma ack becomes 1 and the counter( curr_tc) is loaded from dcon[19:0] register. note that dma ack becomes 1 and remains 1 until it is cleared later. state-3. in this state, sub-fsm handling the atomic operation of dma is initiated. the sub-fsm reads the data from the source address and then writes it to destination address. in this operation, data size and transfer size (single or burst) are considered. this operation is repeated until the counter(curr_tc) becomes 0 in the whole service mode, while performed only once in a singl e service mode. the main fsm (this fsm) counts down the curr_tc when the sub-fsm finishes each of atomic operation. in addition, this main fsm asserts the int req signal when curr_tc becomes 0 and the interrupt setting of dcon[28] register is set to 1. in addition, it clears dma ack if one of the following conditions are met. 1) curr_tc becomes 0 in the whole service mode 2) atomic operation finishes in the single service mode. note that in the single service mode, these three states of main fsm are performed and then stops, and waits for another dma req. and if dma req comes in all three states are repeated. therefore, dma ack is asserted and then de-asserted for each atomic transfer. in contrast, in the whole service mode, main fsm waits at state-3 until curr_tc becomes 0. therefore, dma ack is asserted during all the transfers and then de-asserted when tc reaches 0. however, int req is asserted only if curr_tc becomes 0 regardless of the service mode (single service mode or whole service mode).
s3c2400 risc microprocessor dma 8- 3 external dma dreq/dack protocol there are four types of external dma request/acknowledge protocols. each type defines how the signals like dma request and acknowledge are related to these protocols. basic dma timing the dma service means paired reads and writes cycles during dma operation, which is one dma operation. the figure 8-1 shows the basic timing in the dma operation of the s3c2400. ? the setup time and the delay time of xnxdreq and xnxdack are same in all the modes. ? if the completio n of xnxdreq meets its setup time, it is synchronized twice and then xnxdack is asserted. ? after assertion of xnxdack, dma requests the bus and if it gets the bus it performs its operations. xnxdack is deasserted when dma operation finishes. xsclk xnxdreq xnxdack 9.3ns setup min. 2mclk 9.3ns setup 6.6ns delay 6.8ns delay min. 3mclk read write ~ ~ ~ ~ figure 8-1. basic dma timing diagram
dma s3c2400 risc m icroprocessor 8- 4 demand/handshake mode comparison ? related to the protocol between xnxdreq and xnxdack these are two different modes related to the protocol between xnxdreq and xnxdack. fig. 8-2 shows the differences between these two modes i.e., demand and handshake modes. at the end of one transfer(single/burst transfer), dma checks the state of double-synched xnxdreq. demand mode ? if xnxdreq remains asserted, the next transfer starts immediately. otherwise it waits for xnxdreq to be asserted. handshake mode ? if xnxdreq is deasserted, dma deasserts xnxdack in 2cycles. otherwise it waits until xnxdreq is deasserted. caution : xnxdreq has to be asserted(low) only after the deassertion(high) of xnxdack. xsclk xnxdreq xnxdack min. 2mclk read write ~ ~ ~ ~ 1st transfer 2nd transfer read write ~ ~ ~ ~ actual transfer bus acquisition demand mode 2 cycles xnxdreq xnxdack read write ~ ~ ~ ~ handshake mode min. 2mclk figure 8-2. demand/handshake mode comparison
s3c2400 risc microprocessor dma 8- 5 transfer size ? there are two different transfer sizes; single and burst 4. ? dma holds the bus firmly during the transfer of these chunk of data, thus other bus masters can not get the bus. burst 4 transfer size 4 sequential reads and 4 sequential writes are performed in the burst 4 transfer. note: single transfer size : one read and one write are performed. xsclk xnxdreq xnxdack min. 2mclk 3 cycles read read ~ ~ ~ ~ read read ~ ~ ~ ~ write write ~ ~ ~ ~ write write ~ ~ ~ ~ figure 8-3. burst 4 transfer size
dma s3c2400 risc m icroprocessor 8- 6 examples of possible cases single service, demand mode, single transfer size the assertion of xnxdreq is need for every unit transfer(single service mode), the operation continues while the xnxdreq is asserted(demand mode), and one pair of read and write(single transfer size) is performed. xsclk xnxdreq xnxdack min. 2mclk read write ~ ~ ~ ~ read write ~ ~ ~ ~ figure 8-4. single service, demand mode, single transfer size single service/handshake mode, single transfer size xsclk xnxdreq xnxdack min. 2mclk read write ~ ~ ~ ~ read write ~ ~ ~ ~ figure 8-5. single service, handshake mode, single transfer size whole service/handshake mode, single transfer size xsclk xnxdreq xnxdack double synch read write ~ ~ ~ ~ 3 cycles read write ~ ~ ~ ~ read write ~ ~ ~ ~ 2 cycles 2 cycles figure 8-6. whole service, handshake mode, single transfer size
s3c2400 risc microprocessor dma 8- 7 dma special registers there are seven control registers for each dma channel. (since there are four channels, the total number of control registers is 28.) four of them are to control the dma transfer, and other three are to see the status of dma controller. the details of those registers are as follows. dma initial source register ( disrc ) register address r/w description reset value disrc0 0x14600000 r/w dma 0 initial source register 0x00000000 disrc1 0x14600020 r/w dma 1 initial source register 0x00000000 disrc2 0x14600040 r/w dma 2 initial source register 0x00000000 disrc3 0x14600060 r/w dma 3 initial source register 0x00000000 disrcn bit description initial state loc [30] bit 30 is used to select the location of source. 0 = the source is in the system bus (ahb), 1 = the source is in the peripheral bus (apb) 0 inc [29] bit 29 is used to select the address increment. 0 = increment 1= fixed if it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. if it is 1, the address is not changed after the transfer (in the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer). 0 s_addr [28:0] these bits are the base address (start address) of source data to transfer. this value will be loaded into curr_src only if the curr_src is 0 and the dma ack is 1. 0x00000000
dma s3c2400 risc m icroprocessor 8- 8 dma initial destination register (didst) register address r/w description reset value didst0 0x14600004 r/w dma 0 initial destination register 0x00000000 didst1 0x14600024 r/w dma 1 initial destination register 0x00000000 didst2 0x14600044 r/w dma 2 initial destination register 0x00000000 didst3 0x14600064 r/w dma 3 initial destination register 0x00000000 didstn bit description initial state loc [30] bit 30 is used to select the location of destination. 0 = the destination is in the system bus (ahb). 1 = the destination is in the peripheral bus (apb). 0 inc [29] bit 29 is used to select the address increment. 0 = increment 1= fixed if it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. if it is 1, the address is not changed after the transfer (in the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer). 0 d_addr [28:0] these bits are the base address (start address) of destination for the transfer. this value will be loaded into curr_src only if the curr_src is 0 and the dma ack is 1. 0x00000000
s3c2400 risc microprocessor dma 8- 9 dma control register (dcon) register address r/w description reset value dcon0 0x14600008 r/w dma 0 control register 0x00000000 dcon1 0x14600028 r/w dma 1 control register 0x00000000 dcon2 0x14600048 r/w dma 2 control register 0x00000000 dcon3 0x14600068 r/w dma 3 control register 0x00000000 dconn bit description initial state dmd_hs [30] select one between demand mode and handshake mode. 0 = demand mode is selected 1 = handshake mode is selected. in both modes, dma controller starts its transfer and asserts dack for a given asserted dreq. the difference between two modes is whether it waits for the de-asserted dack or not. in handshake mode, dma controller waits for the de-asserted dreq before starting a new transfer. if it sees the de-asserted dreq, it de-asserts dack and waits for another asserted dreq. in contrast, in the demand mode, dma controller does not wait until the dreq is de-asserted. it just de-asserts dack and then starts another transfer if dreq is asserted. we recommend using handshake mode for external dma request sources to prevent unintended starts of new transfers. 0 sync [29] select dreq/dack synchronization. 0 = dreq and dack are synchronized to pclk (apb clock). 1 = dreq and dack are synchronized to hclk (ahb clock). therefore, devices attached to ahb system bus, this bit has to be set to 1, while those attached to apb system, it should be set to 0. for the devices attached to external system, user should select this bit depending on whether the external system is synchronized with ahb system or apb system. 0 int [28] enable/disable the interrupt setting for curr_tc(terminal count) 0 = curr_tc interrupt is disabled. user has to look the transfer count in the status register. (i.e., polling) 1 = interrupt request is generated when all the transfer is done (i.e., curr_tc becomes 0). 0 tsz [27] select the transfer size of an atomic transfer (i.e., transfer performed at each time dma owns the bus before releasing the bus). 0 = a unit transfer is performed. 1 = a burst transfer of length four is performed. 0
s3c2400 risc microprocessor dma 8- 10 dconn bit description initial state servmode [26] select the service mode between single service mode and whole service mode. 0: single service mode is selected in which after each atomic transfer (single or burst of length four) dma stops and waits for another dma request. 1: whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0. in this mode, additional request is not required. here, note that even in the whole service mode, dma releases the bus after each atomic transfer and then tries to re-get the bus to prevent starving of other bus masters. 0 hwsrcsel [25:24] select dma request source for each dma. dcon0: 00: nxdreq0 01:uart0 10:mmc 11:timer dcon1: 00: nxdreq1 01:uart1 10:i2ssdi 11:spi dcon2: 00:i2ssdo 01:i2ssdi 10:mmc 11:tim er dcon3: 00:usb device 01:mmc 10:spi 11:timer this bits control the 4-1 mux to select the dma request source of each dma. these bits have meanings if and only if h/w request mode is selected by dconn[23]. 00 swhw_sel [23] select the dma source between software (s/w request mode) and hardware (h/w request mode). 0: s/w request mode is selected and dma is triggered by setting sw_trig bit of dmasktrig control register. 1: dma source selected by bit[25:24] is used to trigger the dma operation. 0 reload [22] set the reload on/off option. 0 = auto reload is performed when a current value of transfer count becomes 0 (i.e., all the required transfers are performed). 1 = dma channel(dma req) is turned off when a current value of transfer count becomes 0. the channel on/off bit( dmasktrign[1]) is set to 0(dreq off) to prevent unintended further start of new dma operation 0 dsz [21:20] data size to be transferred. 00 = byte 01 = half word 10 = word 11 = reserved 00 tc [19:0] initial transfer count (or transfer beat). note that the actual number of bytes that are transferred is computed by the following equation: dsz x tsz x tc, where dsz, tsz, and tc represent data size ( dconn[21:20]), transfer size ( dconn[27]), and initial transfer count, respectively. this value will be loaded into curr_src only if the curr_src is 0 and the dma ack is 1. 00000
s3c2400 risc microprocessor dma 8- 11 dma status register (dstat) register address r/w description reset value dstat0 0x1460000c r dma 0 count register 000000h dstat1 0x1460002c r dma 1 count register 000000h dstat2 0x1460004c r dma 2 count register 000000h dstat3 0x1460006c r dma 3 count register 000000h dstatn bit description initial state stat [21:20] status of this dma controller. 00 = it indicates that dma controller is ready for another dma request. 01 = it indicates that dma controller is busy for transfers. 00b curr_tc [19:0] current value of transfer count. note that transfer count is initially set to the value of dconn[19:0] register and decreased by one at the end of every atomic transfer. 00000h
dma s3c2400 risc m icroprocessor 8- 12 dma current source register (dcsrc) register address r/w description reset value dcsrc0 0x14600010 r dma 0 current source register 0x00000000 dcsrc1 0x14600030 r dma 1 current source register 0x00000000 dcsrc2 0x14600050 r dma 2 current source register 0x00000000 dcsrc3 0x14600070 r dma 3 current source register 0x00000000 dcsrcn bit description initial state curr_src [28:0] current source address for dman. 0x00000000 current destination register (dcdst) register address r/w description reset value dcdst0 0x14600014 r dma 0 current destination register 0x00000000 dcdst1 0x14600034 r dma 1 current destination register 0x00000000 dcdst2 0x14600054 r dma 2 current destination register 0x00000000 dcdst3 0x14600074 r dma 3 current destination register 0x00000000 dcdstn bit description initial state curr_dst [28:0] current destination address for dman. 0x00000000
s3c2400 risc microprocessor dma 8- 13 dma mask trigger register (dmasktrig) register address r/w description reset value dmasktrig0 0x14600018 r/w dma 0 mask trigger register 000 dmasktrig1 0x14600038 r/w dma 1 mask trigger register 000 dmasktrig2 0x14600058 r/w dma 2 mask trigger register 000 dmasktrig3 0x14600078 r/w dma 3 mask trigger register 000 dmasktrign bit description initial state stop [2] stop the dma operation. 1 = dma stops as soon as the current atomic transfer ends. if there is no current running atomic transfer, dma stops immediately. the curr_tc, curr_src, curr_dst will be 0. note: due to possible current atomic transfer, ? stop ? may take several cycles. the finish of ? stopping ? operation (i.e., actual stop time) can be detected by waiting until the channel on/off bit( dmasktrign[1]) is set to off. this stop is ? actual stop ? . 0 on_off [1] dma channel on/off bit. 0 = dma channel is turned off. (dma request to this channel is ignored.) 1 = dma channel is turned on and the dma request is handled. this bit is automatically set to off if we set the dconn[22] bit to ? no auto reload ? and/or stop bit of dmasktrign to ? stop ? . note that when dcon[22] bit is "no auto reload", this bit becomes 0 when curr_tc reaches 0. if the stop bit is 1, this bit becomes 0 as soon as the current atomic transfer finishes. note: this bit should not be changed manually during dma operations (i.e., this has to be changed only by using dcon[22] or stop bit.) 0 sw_trig [0] trigger the dma channel in s/w request mode. 1 = it requests a dma operation to this controller. however, note that for this trigger to have effects s/w request mode has to be selected ( dconn[23]) and channel on_off bit has to be set to 1 (channel on). when dma operation starts, this bit is cleared automatically. 0 note: you can freely change the values of disrc register, didst registers, and tc field of dcon register. those changes take effect only after the finish of current transfer (i.e., when curr_tc becomes 0). on the other hand, any change made to other registers and/or fields takes immediate effect. therefore, be careful in changing those registers and fields.
dma s3c2400 risc m icroprocessor 8- 14 notes
s3c2400 risc microprocessor i/o ports 9- 1 9 i/o ports overview s3c2400 has 90 multi-functional input/output port pins. there are seven ports: ? one 18-bit output ports. (port a) ? two 16-bit input/output ports. (port b and c) ? one 11-bit input/output port. (port d) ? one 12-bit input/output port. (port e) ? one 7-bit input/output port. (port f) ? one 10-bit input/output port. (port g) each port can be easily configured by software to meet various system configuration and design requirements. you have to define which function of each pin is used before starting the main program. if the multiplexed functions on a pin are not used, the pin can be configured as i/o ports. the initial pin states, before pin configurations, are configured elegantly to avoid some problems.
i/o ports s3c2400 risc microprocessor 9- 2 table 9-1. s3c2400 port configuration overview port a selectable pin functions pa17 output only ngcs[5] ? ? pa16 output only ngcs[4] ? ? pa15 output only ngcs[3] ? ? pa14 output only ngcs[2] ? ? pa13 output only ngcs[1] ? ? pa12 output only ncas[1] ? ? pa11 output only ncas[0] ? ? pa10 output only scke ? ? pa9 output only a24 ? ? pa8 output only a23 ? ? pa7 output only a22 ? ? pa6 output only a21 ? ? pa5 output only a20 ? ? pa4 output only a19 ? ? pa3 output only a18 ? ? pa2 output only a17 ? ? pa1 output only a16 ? ? pa0 output only a0 ? ?
s3c2400 risc microprocessor i/o ports 9- 3 table 9-1. s3c2400 port configuration overview (continued) port b selectable pin functions pb15 input/output data31 ? ? pb14 input/output data30 ? ? pb13 input/output data29 ? ? pb12 input/output data28 ? ? pb11 input/output data27 ? ? pb10 input/output data26 nss ? pb9 input/output data25 i2ssdi ? pb8 input/output data24 ? ? pb7 input/output data23 ? ? pb6 input/output data22 nrts[1] ? pb5 input/output data21 ncts[1] ? pb4 input/output data20 rxd[1] ? pb3 input/output data19 txd[1] ? pb2 input/output data18 tclk[1] ? pb1 input/output data17 nxbreq ? pb0 input/output data16 nxback ?
i/o ports s3c2400 risc microprocessor 9- 4 table 9-1. s3c2400 port configuration overview (continued) port c selectable pin functions pc15 input /output vd[15] ? ? pc14 input /output vd[14] ? ? pc13 input /output vd[13] ? ? pc12 input /output vd[12] ? ? pc11 input /output vd[11] ? ? pc10 input /output vd[10] ? ? pc9 input /output vd[9] ? ? pc8 input /output vd[8] ? ? pc7 input /output vd[7] ? ? pc6 input /output vd[6] ? ? pc5 input /output vd[5] ? ? pc4 input /output vd[4] ? ? pc3 input /output vd[3] ? ? pc2 input /output vd[2] ? ? pc1 input /output vd[1] ? ? pc0 input /output vd[0] ? ? port d selectable pin functions pd10 input /output nwait ? ? pd9 input /output tclk[0] ? ? pd8 input /output tout[3] ? ? pd7 input /output tout[2] ? ? pd6 input /output tout[1] ? ? pd5 input /output tout[0] ? ? pd4 input /output lend i2ssdi ? pd3 input /output vclk ? ? pd2 input /output vline ? ? pd1 input /output vm ? ? pd0 input /output vframe ? ?
s3c2400 risc microprocessor i/o ports 9- 5 table 9-1. s3c2400 port configuration overview (continued) port e selectable pin functions pe11 input /output nxdreq[1] nxbreq ? pe10 input /output nxdreq[0] ? ? pe9 input /output nxdack[1] nxback ? pe8 input /output nxdack[0] ? ? pe7 input /output eint[7] ? ? pe6 input /output eint[6] ? ? pe5 input /output eint[5] tclk[1] ? pe4 input /output eint[4] nrts[1] ? pe3 input /output eint[3] ncts[1] ? pe2 input /output eint[2] i2ssdi ? pe1 input /output eint[1] nss ? pe0 input /output eint[0] ? ? port f selectable pin functions pf6 input /output clkout ? ? pf5 input /output ncts[0] nxbreq ? pf4 input /output nrts[0] nxback ? pf3 input /output txd[1] iicscl ? pf2 input /output txd[0] ? ? pf1 input /output rxd[1] iicsda ? pf0 input /output rxd[0] ? ? port g selectable pin functions pg9 input /output spiclk mmcclk ? pg8 input /output spimosi iicscl ? pg7 input /output spimiso iicsda ? pg6 input /output mmcdat iicscl ? pg5 input /output mmccmd iicsda ? pg4 input /output mmcclk i2ssdi ? pg3 input /output i2ssdo i2ssdi ? pg2 input /output cdclk ? ? pg1 input /output i2ssclk ? ? pg0 input /output i2slrck ? ? note: the underlined function name is selected just after a reset.
i/o ports s3c2400 risc microprocessor 9- 6
s3c2400 risc microprocessor i/o ports 9- 7 port control descriptions port configuration register (pacon-pgcon) in s3c2400, most pins are multiplexed pins. so, it is determined which function is selected for each pins. the pncon (port control register) determines which function is used for each pin. if pe0 ? pe7 is used for the wakeup signal in power down mode, these ports must be configured in interrupt mode. port data register (padat-pgdat) if ports are configured as output ports, data can be written to the corresponding bit of pndat. if ports are configured as input ports, the data can be read from the corresponding bit of pndat. port pull-up register (pbup-pgup) the port pull-up register controls the pull-up resister enable/disable of each port group. when the corresponding bit is 0, the pull-up resister of the pin is enabled. when 1, the pull-up resister is disabled. if the port pull-up register is enabled then the pull-up resisters work without pin ? s functional setting(input, output, datan, eintn and etc) open drain control register the port open drain control register controls the open drain function enable/disable of 6 pad of 2 port group. when the corresponding bit is 1, the open drain function of the pin is enabled. when 0, the open drain function is disabled. miscellaneous control register this register controls lower two byte data port pull-up resister, hi-z state or previous state in stop mode, usb pad, and clkout selection. external interrupt control register the 8 external interrupts are requested by various signaling methods. the extint register configures the signaling method among the low level trigger, high level trigger, falling edge trigger, rising edge trigger, and both edge trigger for the external interrupt request because each external interrupt pin has a digital filter, the interrupt controller can recognize the request signal that is longer than 3 clocks.
i/o ports s3c2400 risc microprocessor 9- 8 i/o port control register port a control registers (pacon, padat) register address r/w description reset value pacon 0x15600000 r/w configures the pins of port a 0x3ffff padat 0x15600004 r/w the data register for port a undef. pacon bit description pa0 [0] 0 = output 1 = addr0 pa1 [1] 0 = output 1 = addr16 pa2 [2] 0 = output 1 = addr17 pa3 [3] 0 = output 1 = addr18 pa4 [4] 0 = output 1 = addr19 pa5 [5] 0 = output 1 = addr20 pa6 [6] 0 = output 1 = addr21 pa7 [7] 0 = output 1 = addr22 pa8 [8] 0 = output 1 = addr23 pa9 [9] 0 = output 1 = addr24 pa10 [10] 0 = output 1 = scke pa11 [11] 0 = output 1 = ncas[0] pa12 [12] 0 = output 1 = ncas[1] pa13 [13] 0 = output 1 = ngcs[1] pa14 [14] 0 = output 1 = ngcs[2] pa15 [15] 0 = output 1 = ngcs[3] pa16 [16] 0 = output 1 = ngcs[4] pa17 [17] 0 = output 1 = ngcs[5] padat bit description pa[17:0] [17:0] when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
s3c2400 risc microprocessor i/o ports 9- 9 port b control registers (pbcon, pbdat, pbup) register address r/w description reset value pbcon 0x15600008 r/w configures the pins of port b 0xaaaaaaaa pbdat 0x1560000c r/w the data register for port b undef. pbup 0x15600010 r/w pull-up disable register for port b 0x0 pbcon bit description pb0 [1:0] 00 = input 01 = output 10 = data16 11 = nxback pb1 [3:2] 00 = input 01 = outp ut 10 = data17 11 = nxbreq pb2 [5:4] 00 = input 01 = output 10 = data18 11 = tclk[1] pb3 [7:6] 00 = input 01 = output 10 = data19 11 = txd[1] pb4 [9:8] 00 = input 01 = output 10 = data20 11 = rxd[1] pb5 [11:10] 00 = input 01 = output 10 = data21 11 = ncts[1] pb6 [13:12] 00 = input 01 = output 10 = data22 11 = nrts[1] pb7 [15:14] 00 = input 01 = output 10 = data23 11 = reserved pb8 [17:16] 00 = input 01 = output 10 = data24 11 = reserved pb9 [19:18] 00 = input 01 = output 10 = data25 11 = i2ssdi pb10 [21:20] 00 = input 01 = output 10 = data26 11 = nss pb11 [23:22] 00 = input 01 = output 10 = data27 11 = reserved pb12 [25:24] 00 = input 01 = output 10 = data28 11 = reserved pb13 [27:26] 00 = input 01 = output 10 = data29 11 = reserved pb14 [29:28] 00 = input 01 = output 10 = data30 11 = reserved pb15 [31:30] 00 = input 01 = output 10 = data31 11 = reserved
s3c2400 risc microprocessor i/o ports 9- 10 pbdat bit description pb[15:0] [15:0] when the port is configured as input port, the corresponding bit is the pin state. when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. pbup bit description pb[15:0] [15:0] 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
s3c2400 risc microprocessor i/o ports 9- 11 port c control registers (pccon, pcdat, pcup) register address r/w description reset value pccon 0x15600014 r/w configures the pins of port c 0x0 pcdat 0x15600018 r/w the data register for port c undef. pcup 0x1560001c r/w pull-up disable register for port c 0x0 pccon bit description pc0 [1:0] 00 = input 01 = output 10 = vd[0] 11 = reserved pc1 [3:2] 00 = input 01 = output 10 = vd[1] 11 = reserved pc2 [5:4] 00 = input 01 = output 10 = vd[2] 11 = reserved pc3 [7:6] 00 = input 01 = output 10 = vd[3] 11 = reserved pc4 [9:8] 00 = input 01 = output 10 = vd[4] 11 = reserved pc5 [11:10] 00 = input 01 = output 10 = vd[5] 11 = reserved pc6 [13:12] 00 = input 01 = output 10 = vd[6] 11 = reserved pc7 [15:14] 00 = input 0 1 = output 10 = vd[7] 11 = reserved pc8 [17:16] 00 = input 01 = output 10 = vd[8] 11 = reserved pc9 [19:18] 00 = input 01 = output 10 = vd[9] 11 = reserved pc10 [21:20] 00 = input 01 = output 10 = vd[10] 11 = reserved pc11 [23:22] 00 = input 01 = output 10 = vd[11] 11 = reserved pc12 [25:24] 00 = input 01 = output 10 = vd[12] 11 = reserved pc13 [27:26] 00 = input 01 = output 10 = vd[13] 11 = reserved pc14 [29:28] 00 = input 01 = output 10 = vd[14] 11 = reserved pc15 [31:30] 00 = input 01 = output 10 = vd[15] 11 = reserved
s3c2400 risc microprocessor i/o ports 9- 12 pcdat bit description pc[15:0] [15:0] when the port is configured as input port, the corresponding bit is the pin state. when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. pcup bit description pc[15:0] [15:0] 0 = the pull up function attached to the corresponding port pin is enabled. 1 = the pull up function is disabled.
s3c2400 risc microprocessor i/o ports 9- 13 port d control registers (pdcon, pddat, pdup) register address r/w description reset value pdcon 0x15600020 r/w configures the pins of port d 0x0 pddat 0x15600024 r/w the data register for port d undef. pdup 0x15600028 r/w pull-up disable register for port d 0x620 pdcon bit description pd0 [1:0] 00 = input 01 = outpu t 10 = vframe 11 = reserved pd1 [3:2] 00 = input 01 = output 10 = vm 11 = reserved pd2 [5:4] 00 = input 01 = output 10 = vline 11 = reserved pd3 [7:6] 00 = input 01 = output 10 = vclk 11 = reserved pd4 [9:8] 00 = input 01 = output 10 = lend 11 = i2ssdi pd5 (note) [11:10] 00 = input 01 = output 10 = tout[0] 11 = reserved pd6 [13:12] 00 = input 01 = output 10 = tout[1] 11 = reserved pd7 [15:14] 00 = input 01 = output 10 = tout[2] 11 = reserved pd8 [17:16] 00 = input 01 = output 10 = tout[3] 11 = reserved pd9 (note) [19:18] 00 = input 01 = output 10 = tclk[0] 11 = reserved pd10 (note) [21:20] 00 = input 01 = output 10 = nwait 11 = reserved note: pd5, pd9, pd10 are ? pull-up disable ? state at the initial condition. pddat bit description pd[10:0] [10:0] when the port is configured as an input port, the corresponding bit is the pin state. when the port is configured as an output port, the pin state is the same as the corresponding bit. when the port is configured as a functional pin, the undefined value will be read. pdup bit description pd[10:0] [10:0] 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
i/o ports s3c2400 risc microprocessor 9- 14 port e control registers (pecon, pedat) if pe0 - pe7 will be used for wake-up signals at power down mode, the ports will be set in interrupt mode. register address r/w description reset value pecon 0x1560002c r/w configures the pins of port e 0x0 pedat 0x15600030 r/w the data register for port e undef. peup 0x15600034 r/w pull-up disable register for port e 0x003 pecon bit description *pe0 [1:0] 00 = input 01 = output 10 = eint[0] 11 = reserved *pe1 [3:2] 00 = input 01 = output 10 = eint[1] 11 = nss pe2 [5:4] 00 = input 01 = output 10 = eint2] 11 = i2ssdi pe3 [7:6] 00 = input 01 = output 10 = eint[3] 11 = ncts[1] pe4 [9:8] 00 = input 01 = output 10 = eint[4] 11 = nrts[1] pe5 [11:10] 00 = input 01 = output 10 = eint[5] 11 = tclk[1] pe6 [13:12] 00 = input 01 = output 10 = eint[6] 11 = reserved pe7 [15:14] 00 = input 01 = output 10 = eint[7] 11 = reserved pe8 [17:16] 00 = input 01 = output 10 = nxdack[0] 11 = reserved pe9 [19:18] 00 = input 01 = output 10 = nxdack[1] 11 = nxback pe10 [21:20] 00 = input 01 = output 10 = nxdreq[0] 11 = reserved pe11 [23:22] 00 = input 01 = output 10 = nxdreq[1] 11 = nxbreq note: * pd0, pd1 are ? pull-up disable ? state at the initial condition.
s3c2400 risc microprocessor i/o ports 9- 15 pedat bit description pe[11:0] [11:0] when the port is configured as an input port, the corresponding bit is the pin state. when the port is configured as an output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. peup bit description pe[11:0] [11:0] 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
i/o ports s3c2400 risc microprocessor 9- 16 port f control registers (pfcon, pfdat, pfup) register address r/w description reset value pfcon 0x15600038 r/w configures the pins of port f 0x0 pfdat 0x1560003c r/w the data register for port f undef. pfup 0x15600040 r/w pull-up disable register for port f 0x0 pfcon bit description pf0 [1:0] 00 = input 01 = output 10 = rxd[0] 11 = reserved pf1 [3:2] 00 = input 01 = output 10 = rxd[1] 11 = iicsda pf2 [5:4] 00 = input 01 = output 10 = txd[0] 11 = reserved pf3 [7:6] 00 = input 01 = out put 10 = txd[1] 11 = iicscl pf4 [9:8] 00 = input 01 = output 10 = nrts[0] 11 = nxback pf5 [11:10] 00 = input 01 = output 10 = ncts[0] 11 = nxbreq pf6 [13:12] 00 = input 01 = output 10 = clkout 11 = reserved pfdat bit description pf[6:0] [6:0] when the port is configured as an input port, the corresponding bit is the pin state. when the port is configured as an output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. pfup bit description pf[6:0] [6:0] 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
s3c2400 risc microprocessor i/o ports 9- 17 port g control registers (pgcon, pgdat, pgup) register address r/w description reset value pgcon 0x15600044 r/w configures the pins of port g 0x0 pgdat 0x15600048 r/w the data register for port g undef. pgup 0x1560004c r/w pull-up disable register for port g 0x0 pgcon bit description pg0 [1:0] 00 = input 01 = output 10 = i2slrck 11 = reserved pg1 [3:2] 00 = input 01 = output 10 = i2ssclk 11 = reserved pg2 [5:4] 00 = input 01 = output 10 = cdclk 11 = reserved pg3 [7:6] 00 = input 01 = output 10 = i2ssdo 11 = i2ssdi pg4 [9:8] 00 = input 01 = output 10 = mmcclk 11 = i2ssdi pg5 [11:10] 00 = input 01 = output 10 = mmccmd 11 = iicsda pg6 [13:12] 00 = input 01 = output 10 = mmcdat 11 = iicscl pg7 [15:14] 00 = input 01 = output 10 = spimiso 11 = iicsda pg8 [17:16] 00 = input 01 = output 10 = spimosi 11 = iicscl pg9 [19:18] 00 = input 01 = output 10 = spiclk 11 = mmcclk pgdat bit description pg[9:0] [9:0] when the port is configured as an input port, the corresponding bit is the pin state. when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as a functional pin, the undefined value will be read. pgup bit description pg[9:0] [9:0] 0 = the pull up function attached to to the corresponding port pin is enabled. 1 = the pull up function is disabled.
i/o ports s3c2400 risc microprocessor 9- 18 open drain control register (opencr) port f[1], f[3] and port g[8:5] pin ? s open drain mode can be controlled by opencr register. register address r/w description reset value opencr 0x15600050 r/w open-drain enable register 0x0 opencr bit description opc_rxd1 [0] 0 = pf[1] port open-drain mode is disabled 1 = pf[1] port open-drain mode is enabled opc_txd1 [1] 0 = pf[3] port open-drain mode is disabled 1 = pf[3] port open-drain mode is enabled opc_cmd [2] 0 = pg[5] port open-drain mode is disabled 1 = pg[5] port open-drain mode is enabled opc_dat [3] 0 = pg[6] port open-drain mode is disabled 1 = pg[6] port open-drain mode is enabled opc_miso [4] 0 = pg[7] port open-drain mode is disabled 1 = pg[7] port open-drain mode is enabled opc_mosi [5] 0 = pg[8] port open-drain mode is disabled 1 = pg[8] port open-drain mode is enabled
s3c2400 risc microprocessor i/o ports 9- 19 miscellaneous control register (misccr) d[15:0] pin pull-up resister can be controlled by misccr register. in stop mode, the data bus(d[31:0] or d[15:0] is hi-z state. but, because of the characteristics of io pad, the data bus pull-up resisters have to be turned on to reduce the power consumption in stop mode. d[31:16] pin pull-up resisters can be controlled by pbup register. d[15:0] pin pull-up resisters can be controlled by misccr register. in stop mode, memory control signals (a[24:0], ngcs[5:0], nwe, noe, nbe:nwbe:dqm) can be selectable hi-z state or previous state in order to protect memory mal-function by setting the error! bookmark not defined. field in misccr register. pads related usb are controlled by this register for usb host, or for usb device. clkout signal can be selectable fclk, hclk, pclk, mpll clk, or upll clk by setting the clksel field. because of the pad delay, clkout signal doesn ? t have same phase with it ? s original clock source(internal fclk, hclk, pclk, mpll clk, and upll clk) register address r/w description reset value misccr 0x15600054 r/w miscellaneous control register 0x00 misccr bit description spucr0 [0] 0 = data[7:0] port pull-up resister is enabled 1 = data[7:0] port pull-up resister is disabled spucr1 [1] 0 = data[15:8] port pull-up resister is enabled 1 = data[15:8] port pull-up resister is disabled hz@stop [2] 0 = hz @ stop 1 = previous state of pad. usbpad [3] 0 = use pads related usb for usb device 1 = use pads related usb for usb host clksel [6:4] 000 = select mpll clk with clkout pad 001 = select upll clk with clkout pad 010 = select fclk with clkout pad 011 = select hclk with clkout pad 1xx = select pclk with clkout pad note: clkout is prepared to monitor an internal clock situation (on/off status or frequency).
i/o ports s3c2400 risc microprocessor 9- 20 extint (external interrupt control register) the 8 external interrupts can be requested by various signaling methods. the extint register configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. to recognize the level interrupt, the valid logic level on extintn pin must be retained for 40ns at least because of the noise filter. register address r/w description reset value extint 0x15600058 r/w external interrupt control register 0x000000 extint bit description eint0 [2:0] setting the signaling method of the eint0. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint1 [6:4] setting the signaling method of the eint1. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint2 [10:8] setting the signaling method of the eint2. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint3 [14:12] setting the signaling method of the eint3. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint4 [18:16] setting the signaling method of the eint4. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint5 [22:20] setting the signaling method of the eint5. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint6 [26:24] setting the signaling method of the eint6. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered eint7 [30:28] setting the signaling method of the eint7. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered
s3c2400 risc microprocessor i/o ports 9- 21 notes
s3c2400 risc microprocessor pwm timer 10- 1 10 pwm timer overview the s3c2400 has five 16-bit timers. the timer 0, 1, 2, 3 have pwm function (pulse width modulation). timer 4 has an internal timer only with no output pins. timer 0 has a dead-zone generator, which is used with a large current device. timer 0 and timer 1 share an 8-bit prescaler, timers 2 & 3 share the other 8-bit prescaler. each timer has a clock- divider which has 5 different divided signals (1/2, 1/4, 1/8, 1/16, tclk). each timer block receives its own clock signals from the clock-divider, which receives the clock from the corresponding 8-bit prescaler. the 8-bit prescaler is programmable and divides the mux output signal (phclk) according to the loading value which is stored in tcfg0 and tcfg1 registers. the timer count buffer register ( tcntbn) has an initial value which is loaded into the down-counter when the timer is enabled. the timer compare buffer register ( tcmpbn) has an initial value which is loaded into the compare register to be compared with the down-counter value. this double buffering feature of tcntbn and tcmpbn makes the timer generate a stable output when the frequency and duty ratio are changed. each timer has its own 16-bit down-counter which is driven by the timer clock. when the down-counter reaches zero, the timer interrupt request is generated to inform the cpu that the timer operation has been completed. when the timer counter reaches zero, the value of corresponding tcntbn is automatically loaded into the down-counter to continue the next operation. however, if the timer stops, for example, by clearing the timer enable bit of tconn during the timer running mode, the value of tcntbn will not be reloaded into the counter. the value of tcmpbn is used for pwm (pulse width modulation). the timer control logic changes the output level when the down-counter value matches the value of the compare register in the timer control logic. therefore, the compare register determines the turn-on time (or turn-off time) of an pwm output. features ? five 16-bit timers ? two 8-bit prescalers & five 4-bit divider ? programmable duty control of output waveform (pwm) ? auto-reload mode or one-shot pulse mode ? dead-zone generator
pwm timer s3c2400 r isc microprocessor 10- 2 clock divider 5:1 mux dead zone generator tout0 tout1 tout2 control logic0 tcmpb0 tcntb0 control logic1 tcmpb1 tcntb1 5:1 mux clock divider 5:1 mux 5:1 mux control logic2 tcmpb2 tcntb2 tout3 control logic3 tcmpb3 tcntb3 no pin pclk 8-bit prescaler 8-bit prescaler dead zone dead zone tclk0 1/8 1/4 1/16 1/2 tclk1 1/8 1/4 1/16 1/2 5:1 mux control logic4 tcntb4 figure 10-1. 16-bit pwm timer block diagram
s3c2400 risc microprocessor pwm timer 10- 3 pwm timer operation prescaler & divider an 8-bit prescaler and 4-bit divider make the following output frequencies: 4-bit divider settings minimum resolution ( prescaler = 0) maximum resolution ( prescaler = 255) maximum interval ( tcntbn = 65535) 1/2 (pclk = 66 mhz) 0.0303 us (33.0000 mhz) 7.7575 us (128.9063 khz) 0.5084 sec 1/4 (pclk = 66 mhz) 0.0606 us (16.5000 mhz) 15.5151 us (64.4531 khz) 1.0168 sec 1/8 (pclk = 66 mhz) 0.1212 us (8.2500 mhz) 31.0303 us (32.2266 khz) 2.0336 sec 1/16 (pclk = 66 mhz) 0.2424 us (4.1250 mhz) 62.0606 us (16.1133 khz) 4.0671 sec basic timer operation tcmpn 1 0 tcntn 3 3 2 1 0 2 1 0 0 start bit=1 timer is started tcntn=tcmpn auto-reload tcntn=tcmpn timer is stopped toutn command status tcntbn=3 tcntbn=1 manual update=1 auto-reload=1 tcntbn=2 tcntbn=0 manual update=0 auto-reload=1 interrupt request auto-reload interrupt request figure 10-2. timer operations a timer (except the timer ch-5) has tcntbn, tcntn, tcmpbn and tcmpn. tcntbn and tcmpbn are loaded into tcntn and tcmpn when the timer reaches 0. when tcntn reaches 0, the interrupt request will occur if the interrupt is enabled. ( tcntn and tcmpn are the names of the internal registers. the tcntn register can be read from the tcnton register)
pwm timer s3c2400 r isc microprocessor 10- 4 auto-reload & double buffering s3c2400 pwm timers have a double buffering feature, which can change the reload value for the next timer operation without stopping the current timer operation. so, although the new timer value is set, a current timer operation is completed successfully. the timer value can be written into tcntbn (timer count buffer register) and the current counter value of the timer can be read from tcnton (timer count observation register). if tcntbn is read, the read value is not the current state of the counter but the reload value for the next timer duration. the auto-reload is the operation, which copies the tcntbn into tcntn when tcntn reaches 0. the value, written into tcntbn, is loaded to tcntn only when the tcntn reaches to 0 and auto-reload is enabled. if the tcntn is 0 and the auto-reload bit is 0, the tcntn does not operate any further. write tcntbn = 100 write tcntbn = 200 start tcntbn = 150 auto-reload 150 100 100 200 interrupt figure 10-3. example of double buffering feature
s3c2400 risc microprocessor pwm timer 10- 5 timer initialization using manual update bit and inverter bit because an auto-reload operation of the timer occurs when the down counter reaches to 0, a starting value of the tcntn has to be defined by the user at first. in this case, the starting value has to be loaded by the manual update bit. the sequence of starting a timer is as follows; 1) write the initial value into tcntbn and tcmpbn 2) set the manual update bit of the corresponding timer. it is recommended to configure the inverter on/off bit. (whether use inverter or not) 3) set start bit of corresponding timer to start the timer(at the same time, clear the manua l update bit). also, if the timer is stopped by force, the tcntn retains the counter value and is not reloaded from tcntbn. if new value has to be set, manual update has to be done. note whenever tout inverter on/off bit is changed, the toutn logic value will be changed whether or not the timer runs. therefore, it is desirable that the inverter on/off bit is configured with the manual update bit.
pwm timer s3c2400 r isc microprocessor 10- 6 example of a timer operation toutn 1 2 4 6 50 110 40 40 60 20 3 7 9 10 5 8 11 figure 10-4. example of a timer operation the result of the following procedure is shown in figure10-4; 1. enable the auto-reload feature. set the tcntbn as 160 (50+110) and the tcmpbn as 110. set the manual update bit and configure the inverter bit(on/off). the manual update bit sets tcntn and tcmpn to the values of tcntbn and tcmpbn, respectively. and then, set tcntbn and tcmpbn as 80 (40+40) and 40, respectively, to determine the next reload value. 2. set the start bit, provided that manual_update is 0 and inverter is off and auto-reload is on. the timer starts counting down after latency time within the timer resolution. 3. when tcntn has the same value with tcmpn, the logic level of toutn is changed from low to high. 4. when tcntn reaches 0, the interrupt request is generated and tcntbn value is loaded into a temporary register. at the next timer tick, tcntn is reloaded with the temporary register value( tcntbn). 5. in the isr(interrupt service routine), the tcntbn and tcmpbn are set as 80 (20+60) and 60, respectively, which is used for the next duration. 6. when tcntn has the same value as tcmpn, the logic level of toutn is changed from low to high. 7. when tcntn reaches 0, tcntn is reloaded automatically with tcntbn. at the same time, the interrupt request is generated. 8. in the isr (interrupt service routine), auto-reload and interrupt request are disabled to stop the timer. 9. when the value of tcntn is same as tcmpn, the logic level of toutn is changed from low to high. 10. even when tcntn reaches to 0, tcntn is not any more reloaded and the timer is stopped because auto-reload has been disabled. 11. no interrupt request is generated.
s3c2400 risc microprocessor pwm timer 10- 7 pwm (pulse width modulation) write tcmpbn = 60 write tcmpbn = 50 write tcmpbn = 40 write tcmpbn = 30 write tcmpbn = 30 write tcmpbn = next pwm value 60 50 40 30 30 figure 10-5. example of pwm pwm feature can be implemented by using the tcmpbn. pwm frequency is determined by tcntbn. a pwm value is determined by tcmpbn in figure 10-5. for a higher pwm value, decrease the tcmpbn value. for a lower pwm value, increase the tcmpbn value. if an output inverter is enabled, the increment/decrement may be reversed. because of the double buffering feature, tcmpbn, for a next pwm cycle, can be written at any point in the current pwm cycle by isr or something else
pwm timer s3c2400 r isc microprocessor 10- 8 output level control inverter off initial state period 1 period 2 timer stop inverter on figure 10-6. inverter on/off the following methods can be used to maintain tout as high or low.(assume the inverter is off) 1. turn off the auto-reload bit. and then, toutn goes to high level and the timer is stopped after tcntn reaches to 0. this method is recommended. 2. stop the timer by clearing the timer start/stop bi t to 0. if tcntn tcmpn, the output level is high. if tcntn > tcmpn, the output level is low. 3. toutn can be inverted by the inverter on/off bit in tcon. the inverter removes the additional circuit to adjust the output level.
s3c2400 risc microprocessor pwm timer 10- 9 dead zone generator the dead zone is for the pwm control in a power device. this feature is used to insert the time gap between a turn- off of a switching device and a turn on of another switching device. this time gap prohibits the two switching devices turning on simultaneously, even for a very short time. tout0 is the pwm output. ntout0 is the inversion of the tout0. if the dead zone is enabled, the output wave form of tout0 and ntout0 will be tout0_dz and ntout0_dz, respectively. ntout0_dz is routed to the tout1 pin. in the dead zone interval, tout0_dz and ntout0_dz can never be turned on simultaneously. tout0 ntout0 tout0_dz ntout0_dz deadzone interval figure 10-7. the wave form when a dead zone feature is enabled
pwm timer s3c2400 r isc microprocessor 10- 10 dma request mode the pwm timer can generate a dma request at every specific times. the timer keeps dma request signal ( ndma_req) low until the timer receives the ack signal. when the timer receives the ack signal, it makes the request signal inactive. the timer, which generates the dma request, is determined by setting dma mode bits(in tcfg1 register). if one of timers is configured as dma request mode, that timer does not generate an interrupt request. the others can generate interrupt normally. dma mode configuration and dma / interrupt operation dma mode dma request timer0 int timer1 int timer2 int timer3 int timer4 int 0000 no select on on on on on 0001 timer0 off on on on on 0010 timer1 on off on on on 0011 timer2 on on off on on 0100 timer3 on on on off on 0101 timer4 on on on on off 0110 no select on on on on on pclk int4tmp dmareq_en ndma_ack ndma_req int4 1 0 1 figure 10-8. the timer 4 dma mode operation
s3c2400 risc microprocessor pwm timer 10- 11 pwm timer control registers timer configuration register0 (tcfg0) timer input clock frequency = pclk / { prescaler value+1} / {divider value} { prescaler value} = 0-255 {divider value} = 2, 4, 8, 16,tclkn register address r/w description reset value tcfg0 0x15100000 r/w configures the two 8-bit prescalers 0x00000000 tcfg0 bit description initial state reserved [31:24] 0x00 dead zone length [23:16] these 8 bits determine the dead zone length. the 1 unit time of the dead zone length is equal to the 1 unit time of timer 0. 0x00 prescaler 1 [15:8] these 8 bits determine prescaler value for timer 2, 3 and 4 0x00 prescaler 0 [7:0] these 8 bits determine prescaler value for timer 0 and 1 0x00
pwm timer s3c2400 r isc microprocessor 10- 12 timer configuration register1 (tcfg1) register address r/w description reset value tcfg1 0x15100004 r/w 5-mux & dma mode selecton register 0x00000000 tcfg1 bit description initial state reserved [31:24] 00000000 dma mode [23:20] select dma request channel 0000 = no select (all interrupt) 0001 = timer0 0010 = timer1 0011 = timer2 0100 = timer3 0101 = timer4 0110 = reserved 0000 mux 4 [19:16] select mux input for pwm timer4. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk1 0000 mux 3 [15:12] select mux input for pwm timer3. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk1 0000 mux 2 [11:8] select mux input for pwm timer2. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk1 0000 mux 1 [7:4] select mux input for pwm timer1. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk0 0000 mux 0 [3:0] select mux input for pwm timer0. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 01xx = external tclk0 0000
s3c2400 risc microprocessor pwm timer 10- 13 timer control register (tcon) register address r/w description reset value tcon 0x15100008 r/w timer control register 0x00000000 tcon bit description initial state timer 4 auto reload on/off [22] this bit determines auto reload on/off for timer 4. 0 = one-shot 1 = interval mode (auto reload) 0 timer 4 manual update (note) [21] this bit determines the manual update for timer 4. 0 = no operation 1 = update tcntb4 0 timer 4 start/stop [20] this bit determines start/stop for timer 4. 0 = stop 1 = start for timer 4 0 timer 3 auto reload on/off [19] this bit determines auto reload on/off for timer 3. 0 = one-shot 1 = interval mode (auto reload) 0 timer 3 output inverter on/off [18] this bit determines output inverter on/off for timer 3. 0 = inverter off 1 = inverter on for tout3 0 timer 3 manual update (note) [17] this bit determine manual update for timer 3. 0 = no operation 1 = update tcntb3, tcmpb3 0 timer 3 start/stop [16] this bit determines start/stop for timer 3. 0 = stop 1 = start for timer 3 0 timer 2 auto reload on/off [15] this bit determines auto reload on/off for timer 2. 0 = one-shot 1 = interval mode (auto reload) 0 timer 2 output inverter on/off [14] this bit determines output inverter on/off for timer 2. 0 = inverter off 1 = inverter on for tout2 0 timer 2 manual update (note) [13] this bit determines the manual update for timer 2. 0 = no operation 1 = update tcntb2, tcmpb2 0 timer 2 start/stop [12] this bit determines start/stop for timer 2. 0 = stop 1 = start for timer 2 0 timer 1 auto reload on/off [11] this bit determines the auto reload on/off for timer1. 0 = one-shot 1 = interval mode (auto reload) 0 timer 1 output inverter on/off [10] this bit determines the output inverter on/off for timer1. 0 = inverter off 1 = inverter on for tout1 0 timer 1 manual update (note) [9] this bit determines the manual update for timer 1. 0 = no operation 1 = update tcntb1, tcmpb1 0 timer 1 start/stop [8] this bit determines start/stop for timer 1. 0 = stop 1 = start for timer 1 0 note: this bit has to be cleared at next writing.
s3c2400 risc microprocessor pwm timer 10- 14 tcon bit description initial state dead zone enable [4] this bit determines the dead zone operation. 0 = disable 1 = enable 0 timer 0 auto reload on/off [3] this bit determines auto reload on/off for timer 0. 0 = one-shot 1 = interval mode(auto reload) 0 timer 0 output inverter on/off [2] this bit determines the output inverter on/off for timer 0. 0 = inverter off 1 = inverter on for tout0 0 timer 0 manual update (note) [1] this bit determines the manual update for timer 0. 0 = no operation 1 = update tcntb0, tcmpb0 0 timer 0 start/stop [0] this bit determines start/stop for timer 0. 0 = stop 1 = start for timer 0 0 note: this bit has to be cleared at next writing.
s3c2400 risc microprocessor pwm timer 10- 15 timer 0 count buffer register & compare buffer register (tcntb0, tcmpb0) register address r/w description reset value tcntb0 0x1510000c r/w timer 0 count buffer register 0x00000000 tcmpb0 0x15100010 r/w timer 0 compare buffer register 0x00000000 tcmpb0 bit description initial state timer 0 compare buffer register [15:0] setting compare buffer value for timer 0 0x00000000 tcntb0 bit description initial state timer 0 count buffer register [15:0] setting count buffer value for timer 0 0x00000000 timer 0 count observation register (tcnto0) register address r/w description reset value tcnto0 0x15100014 r timer 0 count observation register 0x00000000 tcnto0 bit description initial state timer 0 observation register [15:0] setting count observation value for timer 0 0x00000000
pwm timer s3c2400 r isc microprocessor 10- 16 timer 1 count buffer register & compare buffer register (tcntb1, tcmpb1) register address r/w description reset value tcntb1 0x15100018 r/w timer 1 count buffer register 0x00000000 tcmpb1 0x1510001c r/w timer 1 campare buffer register 0x00000000 tcmpb1 bit description initial state timer 1 compare buffer register [15:0] setting compare buffer value for timer 1 0x00000000 tcntb1 bit description initial state timer 1 count buffer register [15:0] setting count buffer value for timer 1 0x00000000 timer 1 count observation register (tcnto1) register address r/w description reset value tcnto1 0x15100020 r timer 1 count observation register 0x00000000 tcnto1 bit description initial state timer 1 observation register [15:0] setting count observation value for timer 1 0x00000000
s3c2400 risc microprocessor pwm timer 10- 17 timer 2 count buffer register & compare buffer register (tcntb2, tcmpb2) register address r/w description reset value tcntb2 0x15100024 r/w timer 2 count buffer register 0x00000000 tcmpb2 0x15100028 r/w timer 2 campare buffer register 0x00000000 tcmpb2 bit description initial state timer 2 compare buffer register [15:0] setting compare buffer value for timer 2 0x00000000 tcntb2 bit description initial state timer 2 count buffer register [15:0] setting count buffer value for timer 2 0x00000000 timer 2 count observation register (tcnto2) register address r/w description reset value tcnto2 0x1510002c r timer 2 count observation register 0x00000000 tcnto2 bit description initial state timer 2 observation register [15:0] setting count observation value for timer 2 0x00000000
pwm timer s3c2400 r isc microprocessor 10- 18 timer 3 count buffer register & compare buffer register (tcntb3, tcmpb3) register address r/w description reset value tcntb3 0x15100030 r/w timer 3 count buffer register 0x00000000 tcmpb3 0x15100034 r/w timer 3 campare buffer register 0x00000000 tcmpb3 bit description initial state timer 3 compare buffer register [15:0] setting compare buffer value for timer 3 0x00000000 tcntb3 bit description initial state timer 3 count buffer register [15:0] setting count buffer value for timer 3 0x00000000 timer 3 count observation register (tcnto3) register address r/w description reset value tcnto3 0x15100038 r timer 3 count observation register 0x00000000 tcnto3 bit description initial state timer 3 observation register [15:0] setting count observation value for timer 3 0x00000000
s3c2400 risc microprocessor pwm timer 10- 19 timer 4 count buffer register (tcntb4) register address r/w description reset value tcntb4 0x1510003c r/w timer 4 count buffer register 0x00000000 tcntb4 bit description initial state timer 4 count buffer register [15:0] setting count buffer value for timer 4 0x00000000 timer 4 count observation register (tcnto4) register address r/w description reset value tcnto4 0x15100040 r timer 4 count observation register 0x00000000 tcnto4 bit description initial state timer 4 observation register [15:0] setting count observation value for timer 4 0x00000000
pwm timer s3c2400 r isc microprocessor 10- 20 notes
s3c2400 risc microprocessor uart 11- 1 11 uart overview the s3c2400 uart (universal asynchronous receiver and transmitter) unit provides two independent asynchronous serial i/o (sio) ports, each of which can operate in interrupt-based or dma-based mode. in other words, uart can generate an interrupt or dma request to transfer data between cpu and uart. it can support bit rates of up to 115.2k bps. each uart channel contains two 16-byte fifos for receive and transmit. the s3c2400 uart includes programmable baud-rates, infra-red (ir) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking. each uart contains a baud-rate generator, transmitter, receiver and control unit, as shown in figure11-1. the baud- rate generator can be clocked by pclk. the transmitter and the receiver contain 16-byte fifos and data shifters. data, which is to be transmitted, is written to fifo and then copied to the transmit shifter. it is then shifted out by the transmit data pin (txdn). the received data is shifted from the receive data pin (rxdn), and then copied to fifo from the shifter. features ? rxd0,txd0,rxd1,txd1 with dma-based or interrupt-based operation ? uart ch 0 with irda 1.0 & 16-byte fifo ? uart ch 1 with irda 1.0 & 16-byte fifo ? supports handshake transmit / receive
uart s3c2400 risc microprocessor 11- 2 block diagram control unit transmit shifter transmit fifo register(16 byte) transmitter receive fifo register(16 byte) receive shifter receiver peripheral bus txdn clock source rxdn transmit buffer register (transmit fifo and holding register) transmit holding register (non-fifo mode only) receive buffer register (receive fifo and holding register) receive holding register (non-fifo mode only) buad-rate generator figure 11-1. uart block diagram (with fifo)
s3c2400 risc microprocessor uart 11- 3 uart operation the following sections describe the uart operations that include data transmission, data reception, interrupt generation, baud-rate generation, loopback mode, infra-red mode, and auto flow control. data transmission the data frame for transmission is programmable. it consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ulconn). the transmitter can also produce the break condition. the break condition forces the serial output to logic 0 state for one frame transmission time. this block transmits break signal after the present transmission word transmits perfectly. after the break signal transmission, it continously transmits data into the tx fifo (tx holding register in the case of non-fifo mode). data reception like the transmission, the data frame for reception is also programmable. it consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register (ulconn). the receiver can detect overrun error, parity error, frame error and break condition, each of which can set an error flag. ? the overrun error indicates that new data has overwritten the old data before the old data has been read. ? the parity error indicates that the receiver has detected an unexpected parity condition. ? the frame error indicates that the received data does not have a valid stop bit . ? the break condition indicates that the rxdn input is held in the logic 0 state for a duration longer than one frame transmission time. receive time-out condition occurs when it does not receive data during the 3 word time(this interval follows the setting of word length bit) and the rx fifo is not empty in the fifo mode. auto flow control(afc) s3c2400's uart supports auto flow control with nrts and ncts signals, in case it would have to connect uart to uart. if users connect uart to a modem, disable auto flow control bit in umconn register and control the signal of nrts by software. in afc, nrts is controlled by condition of the receiver and operation of transmitter is controlled by the ncts signal. the uart's transmitter transfers the data in fifo only when ncts signal active(in afc, ncts means that the other uart's fifo is ready to receive data). before the uart receives data, nrts has to be activated when its receive fifo has a spare more than 2-byte and has to be inactivated when its receive fifo has a spare under 1-byte(in afc, nrts means that its own receive fifo is ready to receive data). rxd nrts uart a txd ncts uart b txd ncts uart a rxd nrts uart b transmission case in uart a reception case in uart a figure 11-2. uart afc interface
uart s3c2400 risc microprocessor 11- 4 non auto-flow control (controlling nrts and ncts by s/w) example rx operation with fifo 1. select receive mode (interrupt or dma mode) 2. check the value of rx fifo count in ufstatn register. if the value is less than 15, users have to set the value of umconn[0] to '1'(activate nrts), and if it is equal or larger than 15 users have to set the value to '0'(inactivate nrts). 3. repeat item 2. tx operation with fifo 1. select transmit mode (interrupt or dma mode) 2. check the value of umstatn[0]. if the value is '1'(ncts is activated), users write the data to tx fifo register. rs-232c interface if users connect to modem interface (not equal null modem), nrts, ncts, ndsr, ndtr, dcd and nri signals are need. in this case, users control these signals with general i/o ports by s/w because the afc does not support the rs-232c interface.
s3c2400 risc microprocessor uart 11- 5 interrupt/dma request generation each uart of s3c2400 has seven status(tx/rx/error) signals: overrun error, parity error, frame error, break, receive buffer data ready, transmit buffer empty, and transmit shifter empty, all of which are indicated by the corresponding uart status register (utrstatn/uerstatn). the overrun error, parity error, frame error and break condition are referred to as the receive error status, each of which can cause the receive error status interrupt request, if the receive-error-status-interrupt-enable bit is set to one in the control register uconn. when a receive-error-status-interrupt-request is detected, the signal causing the request can be identified by reading uerststn. when the receiver transfers the data of the receive shifter to the receive fifo and the number of received data reaches rx fifo trigger level, rx interrupt is generated, if receive mode in control register is selected as interrupt request or polling mode. in the non-fifo mode, transfering the data of the receive shifter to the receive fifo will cause rx interrupt under the interrupt request and polling mode. when the transmitter transfers data from its transmit fifo to its transmit shifter and the number of data left in transmit fifo reaches tx fifo trigger level, tx interrupt is generated, if transmit mode in control register is selected as interrupt request or polling mode. in the non-fifo mode, transfering data from the transmit fifo to the transmit shifter will cause tx interrupt under the interrupt request and polling mode. if the receive mode and transmit mode in control register are selected as the dman request mode then dman request is occurred instead of rx or tx interrupt in the situation mentioned above. table 11-1. interrupts in connection with fifo type fifo mode non-fifo mode rx interrupt each time receive data reaches the trigger level of receive fifo, the rx interrupt will be generated. when the number of data in fifo does not reaches rx fifo trigger level and does not receive data during 3 word time(this interval follows the setting of word length bit), the rx interrupt will be generated(receive time out). each time receive data becomes full, the receive holding register, generates an interrupt. tx interrupt each time transmit data reaches the trigger level of transmit fifo(tx fifo trigger level), the tx interrupt will be generated. each time transmit data become empty, the transmit holding register generates an interrupt. error interrupt frame error, parity error, and break signal are detected, and will generate an error interrupt. when it gets to the top of the receive fifo without reading out data in it, the error interrupt will be generated(overrun error). all errors generate an error interrupt immediately. however if another error occurs at the same time, only one interrupt is generated.
uart s3c2400 risc microprocessor 11- 6 uart error status fifo uart has the status fifo besides the rx fifo register. the status fifo indicates which data, among fifo registers, is received with an error. the error interrupt will be issued only when the data, which has an error, is ready to read out. to clear the status fifo, the urxhn with an error and uerstatn must be read out. for example, it is assumed that the uart fifo receives a, b, c, d, e characters sequentially and the frame error occurrs while receiving 'b', and the parity error occurs while receiving 'd'. although the actual uart error occurred, the error interrupt will not be generated because the character, which was received with an error, has not been read yet. the error interrupt will occur when the character is read out. time sequence flow error interrupt note #0 when no character is read out ? #1 after a is read out the frame error(in b) interrupt occurs the 'b' has to be read out #2 after b is read out ? #3 after c is read out the parity error(in d) interrupt occurs the 'd' has to be read out #4 after d is read out ? #5 after e is read out ? - - - - - - - - - - - 'e' 'd' 'c' 'b' 'a' rx-fifo break error parity error frame error urxhn error status generator unit status-fifo figure 11-3. a case showing uart receiving 5 characters with 2 errors
s3c2400 risc microprocessor uart 11- 7 baud-rate generation each uart's baud-rate generator provides the serial clock for transmitter and receiver. the source clock for the baud-rate generator can be selected with the s3c2400's internal system clock. the baud-rate clock is generated by dividing the source clock by 16 and a 16-bit divisor specified in the uart baud-rate divisor register (ubrdivn). the ubrdivn can be determined as follows: ubrdivn = (int)(pclk/(bps x 16) ) -1 where the divisor should be from 1 to (2 16 -1). for example, if the baud-rate is 115200 bps and pclk is 40 mhz, ubrdivn is: ubrdivn = (int)(40000000/(115200 x 16) ) -1 = (int)(21.7) -1 = 21 -1 = 20 loop-back mode the s3c2400 uart provides a test mode referred to as the loopback mode, to aid in isolating faults in the communication link. in this mode, the transmitted data is immediately received. this feature allows the processor to verify the internal transmit and to receive the data path of each sio channel. this mode can be selected by setting the loopback-bit in the uart control register (uconn). break condition the break is defined as a continuous low level signal for one frame transmission time on the transmit data output.
uart s3c2400 risc microprocessor 11- 8 ir (infra-red) mode the s3c2400 uart block supports infra-red (ir) transmission and reception, which can be selected by setting the infra-red-mode bit in the uart line control register (ulconn). the implementation of the mode is shown in figure 11-3. in ir transmit mode, the transmit period is pulsed at a rate of 3/16, the normal serial transmit rate (when the transmit data bit is zero); in ir receive mode, the receiver must detect the 3/16 pulsed period to recognize a zero value (refer to the frame timing diagrams shown in figure 11-5 and 11-6 ). irda tx encoder 0 1 0 1 irda rx decoder txd rxd txd irs rxd re uart block figure 11-3. irda function block diagram
s3c2400 risc microprocessor uart 11- 9 start bit stop bit data bits sio frame 0 1 0 1 0 0 1 1 0 1 figure 11-4. serial i/o frame timing diagram (normal uart) 0 start bit stop bit data bits ir transmit frame bit time pulse width = 3/16 bit frame 0 0 0 0 1 1 1 1 1 figure 11-5. infra-red transmit mode frame timing diagram 0 start bit stop bit data bits ir receive frame 0 0 0 0 1 1 1 1 1 figure 11-6. infra-red receive mode frame timing diagram
uart s3c2400 risc microprocessor 11- 10 uart special registers uart line control register there are two uart line control registers, ulcon0 and ulcon1, in the uart block. register address r/w description reset value ulcon0 0x15000000 r/w uart channel 0 line control register 0x00 ulcon1 0x15004000 r/w uart channel 1 line control register 0x00 ulconn bit description initial state reserved [7] 0 infra-red mode [6] the infra-red mode determines whether or not to use the infra-red mode. 0 = normal mode operation 1 = infra-red tx/rx mode 0 parity mode [5:3] the parity mode specifies how parity generation and checking are to be performed during uart transmit and receive operation. 0xx = no parity 100 = odd parity 101 = even parity 110 = parity forced/checked as 1 111 = parity forced/checked as 0 000 number of stop bit [2] the number of stop bits specifies how many stop bits are to be used to signal end-of-frame. 0 = one stop bit per frame 1 = two stop bit per frame 0 word length [1:0] the word length indicates the number of data bits to be transmitted or received per frame. 00 = 5-bits 01 = 6-bits 10 = 7-bits 11 = 8-bits 00
s3c2400 risc microprocessor uart 11- 11 uart control register there are two uart control registers, ucon0 and ucon1, in the uart block. register address r/w description reset value ucon0 0x15000004 r/w uart channel 0 control register 0x00 ucon1 0x15004004 r/w uart channel 1 control register 0x00 uconn bit description initial state tx interrupt type [9] interrupt request type 0 = pulse (interrupt is requested as soon as tx buffer becomes empty in non-fifo mode or tx fifo reaches trigger level in fifo mode) 1 = level (interrupt is requested while tx buffer is empty in non- fifo mode or tx fifo has been being in trigger level in fifo mode) 0 rx interrupt type [8] interrupt request type 0 = pulse (interrupt is requested the instant rx buffer receives the data in non-fifo mode or reaches rx fifo trigger level in fifo mode) 1 = level (interrupt is requested while rx buffer is receiving data in non-fifo mode or reaches rx fifo trigger level in fifo mode) 0 rx time out enable [7] enable/disable rx time out interrupt when uart fifo is enabled. the interrupt is a receive interrupt. 0 = disable 1 = enable 0 rx error status interrupt enable [6] this bit enables the uart to generate an interrupt if an exception, such as a break, frame error, parity error, or overrun error occurs during a receive operation. 0 = do not generate receive error status interrupt 1 = generate receive error status interrupt 0 loop-back mode [5] setting loop-back bit to 1 causes the uart to enter the loop-back mode. this mode is provided for test purposes only. 0 = normal operation 1 = loop-back mode 0 send break signal [4] setting this bit causes the uart to send a break during 1 frame time. this bit is auto-cleared after sending the break signal. 0 = normal transmit 1 = send break signal 0 transmit mode [3:2] these two bits determine which function is currently able to write tx data to the uart transmit buffer register. 00 = disable 01 = interrupt request or polling mode 10 = dma0 request (only for uart0) 11 = dma1 request (only for uart1) 00 receive mode [1:0] these two bits determine which function is currently able to read data from uart receive buffer register. 00 = disable, 01 = interrupt request or polling mode 10 = dma0 request (only for uart0) 11 = dma1 request (only for uart1) 00
uart s3c2400 risc microprocessor 11- 12 uart fifo control register there are two uart fifo control registers, ufcon0 and ufcon1, in the uart block. register address r/w description reset value ufcon0 0x15000008 r/w uart channel 0 fifo control register 0x0 ufcon1 0x15004008 r/w uart channel 1 fifo control register 0x0 ufconn bit description initial state tx fifo trigger level [7:6] these two bits determine the trigger level of transmit fifo. 00 = empty 01 = 4-byte 10 = 8-byte 11 = 12-byte 00 rx fifo trigger level [5:4] these two bits determine the trigger level of receive fifo. 00 = 4-byte 01 = 8-byte 10 = 12-byte 11 = 16-byte 00 reserved [3] 0 tx fifo reset [2] this bit is auto-cleared after resetting fifo 0 = normal 1= tx fifo reset 0 rx fifo reset [1] this bit is auto-cleared after resetting fifo 0 = normal 1= rx fifo reset 0 fifo enable [0] 0 = fifo disable 1 = fifo mode 0 note: when the uart does not reach the fifo trigger level and does not receive data during 3 word time in dma receive mode with fifo, the rx interrupt will be generated (receive time out), and the users should check the fifo status and read out the rest. uart modem control register there are two uart modem control registers, umcon0 and umcon1 in the uart block. register address r/w description reset value umcon0 0x1500000c r/w uart channel 0 modem control register 0x0 umcon1 0x1500400c r/w uart channel 1 modem control register 0x0 umconn bit description initial state reserved [7:5] these bits must be 0's 00 afc (auto flow control) [4] 0 = disable 1 = enable 0 reserved [3:1] these bits must be 0's 00 request to send [0] if afc bit is enabled, this value will be ignored. in this case the s3c2400 will control nrts automatically. if afc bit is disabled, nrts must be controlled by s/w. 0 = 'h' level(inactivate nrts) 1 = 'l' level(activate nrts) 0
s3c2400 risc microprocessor uart 11- 13 uart tx/rx status register there are two uart tx/rx status registers, utrstat0 and utrstat1, in the uart block. register address r/w description reset value utrstat0 0x15000010 r uart channel 0 tx/rx status register 0x6 utrstat1 0x15004010 r uart channel 1 tx/rx status register 0x6 utrstatn bit description initial state transmitter empty [2] this bit is automatically set to 1 when the transmit buffer register has no valid data to transmit and the transmit shift register is empty. 0 = not empty 1 = transmit buffer & shifter register empty 1 transmit buffer empty [1] this bit is automatically set to 1 when the transmit buffer register is empty. 0 =the buffer register is not empty 1 = empty (in non-fifo mode, interrupt or dma is requested. in fifo mode, interrupt or dma is requested, when tx fifo trigger level is set to 00 (empty)) if the uart uses the fifo, users should check tx fifo count bits and tx fifo full bit in the ufstat register instead of this bit. 1 receive buffer data ready [0] this bit is automatically set to 1 whenever the receive buffer register contains valid data, received over the rxdn port. 0 = empty 1 = the buffer register has a received data (in non-fifo mode, interrupt or dma is requested) if the uart uses the fifo, users should check rx fifo count bits and rx fifo full bit in the ufstat register instead of this bit. 0
uart s3c2400 risc microprocessor 11- 14 uart error status register there are two uart rx error status registers, uerstat0 and uerstat1, in the uart block. register address r/w description reset value uerstat0 0x15000014 r uart channel 0 rx error status register 0x0 uerstat1 0x15004014 r uart channel 1 rx error status register 0x0 uerstatn bit description initial state break detect [3] this bit is automatically set to 1 to indicate that a break signal has been received. 0 = no break receive 1 = break receive(interrupt is requested) 0 frame error [2] this bit is automatically set to 1 whenever a frame error occurs during receive operation. 0 = no frame error during receive 1 = frame error(interrupt is requested) 0 parity error [1] this bit is automatically set to 1 whenever a parity error occurs during receive operation. 0 = no parity error during receive 1 = parity error(interrupt is requested) 0 overrun error [0] this bit is automatically set to 1 whenever an overrun error occurs during receive operation. 0 = no overrun error during receive 1 = overrun error(interrupt is requested) 0 note: these bits (uersatn[3:0]) are automatically cleared to 0 when the uart error status register is read.
s3c2400 risc microprocessor uart 11- 15 uart fifo status register there are two uart fifo status registers, ufstat0 and ufstat1, in the uart block. register address r/w description reset value ufstat0 0x15000018 r uart channel 0 fifo status register 0x00 ufstat1 0x15004018 r uart channel 1 fifo status register 0x00 ufstatn bit description initial state reserved [15:10] 0 tx fifo full [9] this bit is automatically set to 1 whenever transmit fifo is full during transmit operation 0 = 0-byte tx fifo data 15-byte 1 = full 0 rx fifo full [8] this bit is automatically set to 1 whenever receive fifo is full during receive operation 0 = 0-byte rx fifo data 15-byte 1 = full 0 tx fifo count [7:4] number of data in tx fifo 0 rx fifo count [3:0] number of data in rx fifo 0
uart s3c2400 risc microprocessor 11- 16 uart modem status register there are two uart modem status registers, umstat0 and umstat1, in the uart block. register address r/w description reset value umstat0 0x1500001c r uart channel 0 modem status register 0x0 umstat1 0x1500401c r uart channel 1 modem status register 0x0 umstat0 bit description initial state reserved [3] 0 delta cts [2] this bit indicates that the ncts input to s3c2400 has changed state since the last time it was read by cpu. (refer to figure 11-7) 0 = has not changed 1 = has changed 0 reserved [1] 0 clear to send [0] 0 = cts signal is not activated(ncts pin is high) 1 = cts signal is activated(ncts pin is low) 0 ncts delta cts read_umstat figure 11-7. ncts and delta cts timing diagram
s3c2400 risc microprocessor uart 11- 17 uart transmit buffer register(holding register & fifo register) utxhn has an 8-bit data for transmission data register address r/w description reset value utxh0 0x15000020(l) 0x15000023(b) w (by byte) uart channel 0 transmit buffer register ? utxh1 0x15004020(l) 0x15004023(b) w (by byte) uart channel 1 transmit buffer register ? utxhn bit description initial state txdatan [7:0] transmit data for uartn ? note: (l): when the endian mode is little endian. (b): when the endian mode is big endian. uart receive buffer register (holding register & fifo register) urxhn has an 8-bit data for received data register address r/w description reset value urxh0 0x15000024(l) 0x15000027(b) r (by byte) uart channel 0 receive buffer register ? urxh1 0x15004024(l) 0x15004027(b) r (by byte) uart channel 1 receive buffer register ? urxhn bit description initial state rxdatan [7:0] receive data for uartn ? note: when an overrun error occurs, the urxhn must be read. if not, the next received data will also make an overrun error, even though the overrun bit of ustatn had been cleared.
uart s3c2400 risc microprocessor 11- 18 uart baud rate division register the value stored in the baud rate divisor register, ubrdiv, is used to determine the serial tx/rx clock rate (baud rate) as follows: ubrdivn = (int)(pclk / (bps x 16) ) -1 where the divisor should be from 1 to (2 16 -1). for example, if the baud-rate is 115200 bps and pclk is 40 mhz , ubrdivn is: ubrdivn = (int)(40000000 / (115200 x 16) ) -1 = (int)(21.7) -1 = 21 -1 = 20 register address r/w description reset value ubrdiv0 0x15000028 r/w baud rate divisior register 0 ? ubrdiv1 0x15004028 r/w baud rate divisior register 1 ? ubrdiv n bit description initial state ubrdiv [15:0] baud rate division value ubrdivn > 0 ?
S3C2400X risc microprocessor usb host 12- 1 12 usb host controller overview s3c2400 supports 2 port usb host interface as follows; open hci rev 1.0 compatible. usb rev1.1 compatible 2 down stream ports. support for both lowspeed and highspeed usb devices hci slave block app_sadr(8) app_sdata(32) hci_data(32) control control ohci regs usb state control list processor block ed&td regs cntl hci master block control ed/td_data(32) ed/td status(32) 64x8 fifo cntl hc_data(8) df_data(8) app_mdata(32) hcm_adr/ data(32) control status control ctrl ctrl rh_data(8) df_data(8) hcf_data(8) addr(6) fifo_data(8) 64x8 fifo root hub & host sie hsie s/m dpll root hub & host sie ohci root hub regs port s/m port s/m port s/m x v r usb 1 x v r usb 2 hci bus ext.fifo status rcf0_regdata(32) txenl txdpls txdmns rcvdata rcvdpls rcvdmns figure 12-1. usb host controller block diagram
usb host s3c2400 r isc microprocessor 12- 2 usb host controller special registers the s3c2400 usb host controller complies with open hci rev 1.0. please refer to open host controller interface rev 1.0 specification for detail information. ohci registers for usb host controller register base address r/w description reset value hcrevision 0x14200000 ? control and status group ? hccontrol 0x14200004 ? ? hccommonstatus 0x14200008 ? ? hcinterruptstatus 0x1420000c ? ? hcinterruptenable 0x14200010 ? ? hcinterruptdisable 0x14200014 ? ? hchcca 0x14200018 ? memory pointer group ? hcperiodcuttented 0x1420001c ? ? hccontrolheaded 0x14200020 ? ? hccontrolcurrented 0x14200024 ? ? hcbulkheaded 0x14200028 ? ? hcbulkcurrented 0x1420002c ? ? hcdonehead 0x14200030 ? ? hcrminterval 0x14200034 ? frame counter group ? hcfmremaining 0x14200038 ? ? hcfmnumber 0x1420003c ? ? hcperiodicstart 0x14200040 ? ? hclsthreshold 0x14200044 ? ? hcrhdescriptora 0x14200048 ? root hub group ? hcrhdescriptorb 0x1420004c ? ? hcrhstatus 0x14200050 ? ? hcrhportstatus1 0x14200054 ? ? hcrhportstatus2 0x14200058 ? ?
s3c2400 risc microprocessor usb device 13- 1 13 usb device overview usb function controller is designed to provide a high performance full speed function controller solution with dma i/f.usb function controller allows bulk transfer with dma, interrupt transfer and control transfer. the integrated on-chip functions are as follows: ? full speed usb function controller compatible with the usb specification version 1.1 ? dma interface for bulk transfer ? 5 endpoint with fifo ep0: 16byte (dual port asynchronous ram) ep1: 64byte in fifo (single port asynchronous ram): interrupt and dma ep2: 64byte in fifo (single port asynchronous ram): interrupt ep3: 64byte out fifo (single port asynchronous ram): interrupt and dma ep4: 64byte out fifo (single port asynchronous ram): interrupt ? integrated usb transceiver ( asic usb pad) features ? fully compliant to usb specification version 1.1 ? full speed (12mbps) device ? integrated usb transceiver (asic usb pad) ? supports control, interrupt and bulk transfer ? 5 endpoint with fifo: one bi-directional control endpoint with 16 byte fifo (ep0) two receive bulk endpoint with 64 byte fifo (ep1, ep2) two transmit bulk endpoint with 64 byte fifo (ep3, ep4) ? supports dma interface for receive and transmit bulk endpoints. (ep1, ep2, ep3, ep4) ? independent 64byte receive and tra nsmit fifo to maximize throughput ? support suspend and remote wake-up function ? operating frequency: 48mhz ? not support iso transfer
usb device s3c2400 risc microprocessor 13- 2 sie rt_vp_out rt_vm_in rt_vp_in rxd rt_uxsuspend rt_ux_oen rt_vm_out mc_addr[13:0] siu gfi fifos mcu & dma i/f mc_data_in[31:0] mc_data_out[31:0] usb_clk sys_clk sys_resetn mc_wr wr_rdn mc_csn mc_intr dreqn dackn power detect vout vin figure 13-1. usb device block diagram
S3C2400X01 risc microprocessor usb device 13- 3 usb device special registers this section describes the detail functionality about register set usb device. all special function register is word access. reserved bit is zero. all register must be set after host reset signaling. function addres register (func_addr_reg) this register maintains the usb device address assigned by the host. the s3c2400 writes the value received through a set_address descriptor to this register. this address is used for the next token. register address r/w description reset value func_addr_reg 0x15200140 r/w function address register 0x00000000 func_addr_reg bit mcu usb description initial state reserved [31:8] r 0 addr_update [7] set r /clear the mcu sets this bit whenever it updates the function_addr field in this register. this bit will be cleared by usb when data_end bit in ep0_csr register. 0 function_addr [6:0] r/w r the mcu write the unique address, assigned by host, to this field. 0000000
usb device s3c2400 risc microprocessor 13- 4 power management register (pwr_reg) this register is power control register in usb block. register address r/w description reset value pwr_reg 0x15200144 r/w power management register 0x00000000 func_addr bit mcu usb description initial state reserved [31:9] 0 clk_mask [8] r/w r the mcu sets this bit to mask usb clock: 0 = normal operation, 1 = usb clock mask clear method : the mcu writes ? high ? on the mcu_reset(bit [7]). mcu_reset [7] w r the mcu sets this bit to reset usb: 0 = normal operation, 1 = s/w reset clear method: the mcu write 'low' on this bit. 0 ep0_flush [6] r/w r the mcu sets this bit to flush ep0 fifo 0 vbus_status [5] r w vbus monitoring bit 0 reserved [4] ? ? 0 usb_reset [3] r set the usb sets this bit if reset signaling is received from the host. this bit remains set as long as reset signaling persists on the bus 0 mcu_resume [2] w r /clear the mcu sets this bit for mcu resume. the usb generates the resume signaling depending resume con register, while this bit is set in suspend mode. suspend_mode [1] r set /clear this bit can be set by usb, automatically when the device enter into suspend mode. it can be cleared under the mcu or usb resume conditions. 0 suspend_en [0] r/w r suspend mode enable control bit: 0 = disable (default) 1 = enable disables masked suspend mode 0
S3C2400X01 risc microprocessor usb device 13- 5 interrupt register (int_reg) these registers act as status registers for the mcu when there is an interrupt event. the bits in these registers are cleared by the mcu by writing a 1(not "0") to each bit. once the mcu is interrupted, mcu should read the contents of interrupt-related registers and write back to clear the contents if it is necessary. register address r/w description reset value int_reg 0x15200148 r interrupt pending/clear register 0x00000000 int_reg bit mcu usb description initial state error interrupt [8] r /clear set error monitoring interrupt source. it can be set under the following conditions: 1. crc error 2. bit stuff error 0 reset interrupt [7] r /clear set reset interrupt it can be set under the following conditions: 1. usb reset 2. mcu reset 0 resume interrupt [6] r /clear set the usb sets this bit, when it receives the resume signaling (resume command in usb bus), while in suspend mode. if the resume is due to a usb reset, then the mcu is first interrupted into a resume interrupt. 0 suspend interrupt [5] r /clear set the usb sets this bit when it receives the suspend signaling. this bit is set whenever there is no activity during 3ms on the usb bus. thus, if the mcu does not stop the clock after the first suspend interrupt, that it will be continually to be interrupted every 3ms as long as there is no activity on the usb bus. by default, this interrupt is masked. 0 ep4 interrupt [4] r /clear set endpoint4 interrupt: 1. sets out_pkt_rdy bit.(ep4_out_csr1[0]) 2. sets sent_stall bit.(ep4_out_csr1[6]) 0 ep3 interrupt [3] r /clear set endpoint3 interrupt: 1. sets out_pkt_rdy bit.(ep3_out_csr1[0]) 2. sets sent_stall bit.(ep3_out_csr1[6]) 0 ep2 interrupt [2] r /clear set endpoint2 interrupt: 1. in_pkt_rdy is cleared.(ep2_in_csr1[0]) 2. fifo is flushed.(ep2_in_csr[2]) 0 ep1 interrupt [1] r /clear set endpoint1 interrupt: 1. in_pkt_rdy is cleared.(ep1_in_csr1[0]) 2. fifo is flushed.(ep1_in_csr[2]) 0 ep0 interrupt [0] r /clear set endpoint0 interrupt: 1. out_pkt_rdy bit (d0) is set.(ep0_csr[0]) 2. in_pkt_rdy bit (d1) is cleared.(ep0_csr[1]) 3. sent_stall bit (d2) is set.(ep0_csr[2]) 4. setup_end bit (d4) is set.(ep0_csr[4]) 5. data_end bit is cleared.(ep0_csr[3]) (indicates end of control transfer) 0
usb device s3c2400 risc microprocessor 13- 6 interrupt mask register (int_mask_reg) this register can mask interrupt(except resume interrupt). register address r/w description reset value int_mask_reg 0x1520014c r/w determines which interrupt is masked. the masked interrupt will not be serviced. 0 = interrupt is available 1 = interrupt is masked 0x033f int_mask_reg bit mcu usb description initial state reserved [31:10] 0 crc_mask [9] r/w r crc error interrupt mask bit: 0 = interrupt enable 1 = masked 1 bit_stuff_mask [8] r/w r bit_stuff error interrupt mask bit: 0 = interrupt enable 1 = masked 1 reset_mask [7] r/w r reset interrupt mask bit: 0 = interrupt enable 1 = masked 0 reserved [6] 0 suspend_mask [5] r/w r suspend interrupt mask bit: 0 = interrupt enable 1 = masked 1 ep4_mask [4] r/w r ep4 interrupt mask bit: 0 = interrupt enable 1 = masked 1 ep3_mask [3] r/w r ep3 interrupt mask bit: 0 = interrupt enable 1 = masked 1 ep2_mask [2] r/w r ep2 interrupt mask bit: 0 = interrupt enable 1 = masked 1 ep1_mask [1] r/w r ep1 interrupt mask bit: 0 = interrupt enable 1 = masked 1 ep0_mask [0] r/w r ep0 interrupt mask bit: 0 = interrupt enable 1 = masked 1
S3C2400X01 risc microprocessor usb device 13- 7 frame number register (fpame_num_reg) when host transfer usb packet, there is frame number in sof(start of frame). the usb catch this frame number and load it into this register, automatically. register address r/w description reset value frame_num_reg 0x15200150 r frame number register 0x00000000 frame_num_reg bit mcu usb description initial state reserved [31:11] 0 frame_num [10:0] r w frame number value 00000000000 resume signal control register (resume_con_reg) this register can control resume signal length. 5-bit down counts. register address r/w description reset value resume_con_reg 0x15200154 r/w resume signal control register 0x000a resume_con_reg bit mcu usb description initial state reserved [31:5] 0 resume_con [4:0] r/w r the value of these 5-bits means the length of resume signal. the unit is mili-second. 00000 = can not be used 00001 = 1 ms 00010 = 2 ms 00011 = 3 ms 00100 = 4 ms 00101 = 5 ms 00110 = 6 ms 00111 = 7 ms 01000 = 8 ms 01001 = 9 ms 01010 = 10 ms 01011 = 11 ms 01100 = 12 ms 01101 = 13 ms 01110 = 14 ms 01111 = 15 ms 10000 = 16 ms 10001 = 17 ms 10010 = 18 ms 10011 = 19 ms 10100 = 20 ms 10101 = 21 ms 10110 = 22 ms 10111 = 23 ms 11000 = 24 ms 11001 = 25 ms 11010 = 26 ms 11011 = 27 ms 11100 = 28 ms 11101 = 29 ms 11110 = 30 ms 11111 = 31 ms 01010
usb device s3c2400 risc microprocessor 13- 8 end point0 control status register (ep0_csr) register address r/w description reset value ep0_csr 0x15200160 r/w clock generator control register 0x00000000 ep0_csr bit mcu usb description initial state reserved [31:8] 0 serviced_setup _end [7] w clear the mcu should write a "1" to this bit to clear setup_end 0 serviced_out_p kt_rdy [6] w clear the mcu should write a "1" to this bit to clear out_pkt_rdy 0 send_stall [5] r/w clear the mcu should writes a "1" to this bit at the same time it clears out_pkt_rdy, if it decodes an invalid token. 0 = finish the stall condition 1 = the usb issues a stall and shake to the current control transfer. 0 setup_end [4] r set the usb sets this bit when a control transfer ends before data_end is set. when the usb sets this bit, an interrupt is generated to the mcu. when such a condition occurs, the usb flushes the fifo and invalidates mcu access to the fifo. 0 data_end [3] set clear the mcu sets this bit below conditions: 1. after loading the last packet of data into the fifo, at the same time in_pkt_rdy is set. 2. while it clears out_pkt_rdy after unloading the last packet of data. 3. for a zero length data phase. 0 sent_stall [2] clear set the usb sets this bit if a control transaction is stopped due to a protocol violation. an interrupt is generated when this bit is set. the mcu should write "0" to clear this bit. 0 in_pkt_rdy [1] set clear the mcu sets this bit after writing a packet of data into ep0 fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so as the mcu to load the next packet. for a zero length data phase, the mcu sets data_end at the same time. 0 out_pkt_rdy [0] r set the usb sets this bit once a valid token is written to the fifo. an interrupt is generated when the usb sets this bit. the mcu clears this bit by writing a "1" to the serviced_out_pkt_rdy bit. 0
S3C2400X01 risc microprocessor usb device 13- 9 end point0 max packet register (ep0_maxp) register address r/w description reset value ep0_maxp 0x15200164 r/w end point0 max packet register 0x00000001 ep0_maxp bit mcu usb description initial state reserved [31:2] 0 ep0_maxp [1:0] r/w r 00: maxp = 0 01: maxp = 8 10: maxp = 16 01 end point0 out write count register (ep0_out_cnt) this register has the number of bytes consist of one packet. initially, out write count register should keep the number of bytes consisting one packet and mcu should fetches number of bytes as many bytes as this register value indicates. register address r/w description reset value ep0_out_cnt 0x15200168 r/w end point0 out write count register 0x00000000 ep0_out_cnt bit mcu usb description initial state reserved [31:5] 0 out_cnt [4:0] r/w r ep0 out write count value 00000 end point0 fifo read/write register (ep0_fifo) end point0 is for input or output to host. to access ep0 fifo, the mcu should access fifo through ep0_fifo register. lower 8-bit is valid. register address r/w description reset value ep0_fifo 0x1520016c r/w end point0 fifo read/write register 0x000000xx ep0_fifo bit mcu usb description initial state reserved [31:8] 0 fifo_data [7:0] r/w r/w ep0 fifo data values 0xxx
usb device s3c2400 risc microprocessor 13- 10 end point in control status register register address r/w description reset value ep1_in_csr 0x15200180 r/w end point1 in control status register 0x00000000 ep2_in_csr 0x15200190 r/w end point2 in control status register 0x00000000 epn_in_csr bit mcu usb description initial state reserved [31:8] 0 auto_set [7] r/w r in case of single packet mode, if the packet size is same as fifo size, in_pkt_rdy bit can be set automatically (auto_set=1) when mcu write a packet data into fifo. this is a special feature in case that the single packet size is same as fifo size. if it's not this case, mcu should set in_pkt_rdy as explained in epn_in_csr register. 0 dma_ipr_in_mask [6] r/w r this bit determines whether the interrupt should be issued, or not, when the ep1 in_pkt_rdy condition happens. this is only useful for dma mode. 0 = interrupt enable, 1 = interrupt masking 0 clr_data_toggle [5] r/w r/ clear this bit can be used in set-up procedure. 0 = there are alternation of data0 and data1. 1 = the data toggle bit is cleared and pid in packet will maintain data0. 0 sent_stall [4] r/ clear set the usb sets this bit when an in token issues a stall handshake, after the mcu sets send_stall bit to start stall handshaking. when the usb issues a stall handshake, in_pkt_rdy is cleared. 0 send_stall [3] w/r r 0 = the mcu clears this bit to finish the stall condition. 1 = the mcu issues a stall and shake to the usb. 0
s3c2400 risc microprocessor usb device 13- 11 epn_in_csr bit mcu usb description initial state fifo_flush [2] w/ clear clear the mcu sets this bit if it intends to flush the packet in input-related fifo. this bit is cleared by the usb when the fifo is flushed. the mcu is interrupted when this happens. if a token is in process, the usb waits until the transmission is complete before fifo flushing. if two packets are loaded into the fifo, only first packet (the packet is intended to be sent to the host) is flushed, and the corresponding in_pkt_rdy bit is cleared 0 reserved [1] 0 in_pkt_rdy [0] set/ r clear the mcu sets this bit after writing a packet data into the fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit so as the mcu to load the next packet. while this bit is set by mcu after writing a packet data into the fifo, the mcu will not be able to write a new packet data to the fifo without clearing by usb. if the send_stall bit is set by the mcu, this bit also cannot be set. 0
usb device s3c2400 risc microprocessor 13- 12 end point in max packet register register address r/w description reset value ep1_in_maxp 0x15200184 r/w end point1 in max packet register 0x00000001 ep2_in_maxp 0x15200194 r/w end point2 in max packet register 0x00000001 epn_in_maxp bit mcu usb description initial state reserved [31:4] 0 in_maxp [3:0] r/w r 0000 : maxp = 0 0001 : maxp = 8 0010 : maxp = 16 0011 : maxp = 24 0100 : maxp = 32 0101 : maxp = 40 0110 : maxp = 48 0111 : maxp = 56 1000 : maxp = 64 0001 end point in fifo write register end point1 or end point2 is for output to host. to access ep1 fifo or ep2 fifo, the mcu should access fifo through ep1_fifo register or ep2_fifo register. lower 8-bit is valid. register address r/w description reset value ep1_fifo 0x15200188 w end point1 fifo write register 0x000000xx ep2_fifo 0x15200198 w end point2 fifo write register 0x000000xx epn_fifo bit mcu usb description initial state reserved [31:8] 0 in_fifo_data [7:0] w r in fifo data value 0xxx
S3C2400X01 risc microprocessor usb device 13- 13 end point out control status register register address r/w description reset value ep3_out_csr 0x152001a0 r/w end point3 out control status register 0x00000000 ep4_out_csr 0x152001b0 r/w end point4 out control status register 0x00000000 epn_out_csr bit mcu usb description initial state reserved [31:8] 0 auto_clr [7] r/w r if mcu set, whenever the mcu reads data from the out fifo, out_pkt_rdy will automatically be cleared by the logic, without any intervention from mcu. 0 dma_opr_int _mask [6] r/w r this bit determines whether the interrupt should be issued, or not, when the ep3 out_pkt_rdy condition happens. this is only useful for dma mode 0 = interrupt enable 1 = interrupt masking 0 clr_data _toggle [5] r/w clear when the mcu writes a 1 to this bit, the data toggle sequence bit is reset to data0. 0 sent_stall [4] clear /r set the usb sets this bit when an out token is ended with a stall handshake. the usb issues a stall handshake to the host if it sends more than maxp data for the out token. 0 send_stall [3] r/w r 0 = the mcu clears this bit to end the stall condition handshake, in pkt rdy is cleared. 1 = the mcu issues a stall handshake to the usb. the mcu clears this bit to end the stall condition handshake, in pkt rdy is cleared. 0 fifo_flush [2] r/w clear the mcu write a 1 to flush the fifo. this bit can be set only when out_pkt_rdy (d0) is set. the packet due to be unloaded by the mcu will be flushed. 0 reserved [1] 0 out_pkt_rdy [0] r/ clear set the usb sets this bit after it has loaded a packet of data into the fifo. once the mcu reads the packet from fifo, this bit should be cleared by mcu. (write a "0") 0
usb device s3c2400 risc microprocessor 13- 14 end point out max packet register register address r/w description reset value ep3_out_maxp 0x152001a4 r/w end point3 out max packet register 0x00000001 ep4_out_maxp 0x152001b4 r/w end point4 out max packet register 0x00000001 epn_in_maxp bit mcu usb description initial state reserved [31:4] 0 out_maxp [3:0] r/w r 0000 : maxp = 0 0001 : maxp = 8 0010 : maxp = 16 0011 : maxp = 24 0100 : maxp = 32 0101 : maxp = 40 0110 : maxp = 48 0111 : maxp = 56 1000 : maxp = 64 0001 end point out write count register this register has the number of bytes consist of one packet. initially, out write count register should keep the number of bytes consisting one packet and mcu should fetches number of bytes as many bytes as this register value indicates. register address r/w description reset value ep3_out_cnt 0x152001a8 r end point3 out write count register 0x00000000 ep4_out_cnt 0x152001b8 r end point4 out write count register 0x00000000 epn_out_cnt bit mcu usb description initial state reserved [31:7] 0 out_cnt [6:0] r w out write count value 0000000
S3C2400X01 risc microprocessor usb device 13- 15 end point fifo read register end point3 or end point4 is for output to mcu. to access ep3 fifo or ep4 fifo, the mcu should access fifo through ep3_fifo register or ep4_fifo register. lower 8-bit is valid. register address r/w description reset value ep3_fifo 0x152001ac r end point3 fifo read register 0x000000xx ep4_fifo 0x152001bc r end point4 fifo read register 0x000000xx epn_fifo bit mcu usb description initial state reserved [31:8] 0 out_fifo_data [7:0] r w out fifo data value 0xxx dma interface control register (dma_con) register address r/w description reset value dma_con 0x152001c0 r/w dma interface control register 0x00000000 clkcon bit mcu usb description initial state reserved [31:8] 0 in_run_ob [7] r w in dma run observation 0 state [6:4] r w dma state monitoring 0 demand_mode [3] r/w r demand mode enable 0 = disable 1 = enable 0 out_dma_run [2] r/w clear this bit is used to start dma operation for end point3 0 = stop 1 = run 0 in_dma_run [1] r/w clear this bit is used to start dma operation for end point1 0 = stop 1 = run 0 dma_mode_en [0] r/w r this bit is used to set dma mode 0 = interrupt mode 1 = dma mode for bulk endpoint 0
usb device s3c2400 risc microprocessor 13- 16 dma unit counter register (dma_unit) 8-bit counter to setting dma transfer unit. register address r/w description reset value dma_unit 0x152001c4 r/w dma transfer unit counter base register 0x00000000 dma_unit bit mcu usb description initial state unit_cnt [7:0] r/w r dma transfer unit counter value 0x00 dma fifo counter register (dma_fifo) this register has byte size in fifo to be transferred by dma. in case of ep3 as soon as out_str_dma_run enable, the value in out fifi write count register1 will be loaded in this register automatically. in case of ep1, the mcu should set proper value by s/w. register address r/w description reset value dma_fifo 0x152001c8 r/w dma transfer fifo counter base register 0x00000000 dma_fifo bit mcu usb description initial state reserved [31:8] 0 fifo_cnt [7:0] r/w r dma transfer fifo counter value 0x00 dma tx counter register (dma_tx) this register (24-bit) should have total number of bytes to be transferred using dma. register address r/w description reset value dma_tx 0x152001cc r/w dma total transfer counter base register 0x00000000 dma_tx bit mcu usb description initial state reserved [31:24] 0 tx_cnt [23:0] r/w r dma total transfer count value 0x000000
S3C2400X01 risc microprocessor usb device 13- 17 test mode control register (test_mode) don't write this register in normal operation. register address r/w description reset value test_mode 0x152001f4 w test mode control register 0x00000000 test_mode bit mcu usb description initial state reserved [31:2] 0 ep1234_mem _test [1] w r the mcu sets this bit to test ep1, ep2, ep3, and ep4 fifo memory. this is set, and then the mcu can access ep1, ep2, ep3, and ep4 fifo memory directly. 0 = test disable (normal operation mode) 1 = test enable 0 ep0_mem_test [0] w r the mcu sets this bit to test ep0 fifo memory. this is set, and then the mcu can access ep0 fifo memory directly. 0 = test disable (normal operation mode) 1 = test enable 0 in packet number control register (in_con_reg) this register can control number of in packet terms of sof(start of frame) register address r/w description reset value in_con_reg 0x152001f8 w in packet number control register 0x00ff in_con_reg bit mcu usb description initial state reserved [31:8] 0 in_con_mask [7] w r in con function masking 0 = enable 1 = masked (normal operation mode) 1 in_con [6:0] w r this data is number of in packet terms of sof. if this data were 3, usb device responses nak to 4th in packet. 1111111
usb device s3c2400 risc microprocessor 13- 18 notes
s3c2400 risc microprocessor interrupt controller 14- 1 14 interrupt controller overview the interrupt controller in s3c2400 receives the request from 32interrupt sources. these interrupt sources are provided by internal peripheral such as the dma controller, uart and iic, etc. in these interrupt sources, the uart0 and uart1 error interrupts are ' or'ed to the interrupt controller. the role of the interrupt controller is to ask for the fiq or irq interrupt requests to the arm920t core after the arbitration process when there are multiple interrupt requests from internal peripherals and external interrupt request pins. the arbitration process is performed by the hardware priority logic and the result is written to the interrupt pending register and users notice that register to know which interrupt has been requested. srcpnd mask mode priority intpnd irq fiq figure 14-1. interrupt process diagram
interrupt controller s3c2400 risc micr oprocessor 14- 2 interrupt controller operation f-bit and i-bit of psr (program status register) if the f-bit of psr (program status register in arm920t cpu) is set to 1, the cpu does not accept the fiq (fast interrupt request) from the interrupt controller. if i-bit of psr (program status register in arm920t cpu) is set to 1, the cpu does not accept the irq (interrupt request) from the interrupt controller. so, to enable the interrupt reception, the f-bit or i-bit of psr has to be cleared to 0 and also the corresponding bit of intmsk has to be set to 0. interrupt mode arm920t has 2 types of interrupt mode, fiq or irq. all the interrupt sources determine the mode of interrupt to be used at interrupt request. interrupt pending register S3C2400X01 has two interrupt pending resisters. the one is source pending register(srcpnd), the other is interrupt pending register(intpnd). these pending registers indicate whether or not an interrupt request is pending. when the interrupt sources request interrupt service the corresponding bits of srcpnd register are set to 1, at the same time the only one bit of intpnd register is set to 1 automatically after arbitration process. if interrupts are masked, the corresponding bits of srcpnd register are set to 1, but the bit of intpnd register is not changed. when a pending bit of intpnd register is set, the interrupt service routine starts whenever the i-flag or f-flag is cleared to 0. the srcpnd and intpnd registers can be read and written, so the service routine must clear the pending condition by writing a 1 to the corresponding bit in srcpnd register first and then clear the pending condition in intpnd registers same method. interrupt mask register indicates that an interrupt has been disabled if the corresponding mask bit is 1. if an interrupt mask bit of intmsk is 0, the interrupt will be serviced normally. if the corresponding mask bit is 1 and the interrupt is generated, the source pending bit will be set.
s3c2400 risc microprocessor interrupt controller 14- 3 interrupt sources interrupt controller supports 32 interrupt sources as shown in below table. two uart error interrupt requests are ored to provide a single interrupt source to the interrupt controller. sources descriptions arbiter group int_adc adc eoc interrupt arb5 int_rtc rtc alarm interrupt arb5 int_utxd1 uart1 transmit interrupt arb5 int_utxd0 uart0 transmit interrupt arb5 int_iic iic interrupt arb4 int_usbh usb host interrupt arb4 int_usbd usb device interrupt arb4 int_urxd1 uart1 receive interrupt arb4 int_urxd0 uart0 receive interrupt arb4 int_spi spi interrupt arb4 int_mmc mmc interrupt arb 3 int_dma3 dma channel 3 interrupt arb3 int_dma2 dma channel 2 interrupt arb3 int_dma1 dma channel 1 interrupt arb3 int_dma0 dma channel 0 interrupt arb3 reserved reserved for future use arb3 int_uerr0/1 uart0/1 error interrupt arb2 int_timer4 timer4 interrupt arb2 int_timer3 timer3 interrupt arb2 int_timer2 timer2 interrupt arb2 int_timer1 timer1 interrupt arb 2 int_timer0 timer0 interrupt arb2 int_wdt watch-dog timer interrupt arb1 int_tick rtc time tick interrupt arb1 eint7 external interrupt 7 arb1 eint6 external interrupt 6 arb1 eint5 external interrupt 5 arb1 eint4 external interrupt 4 arb1 eint3 external interrupt 3 arb0 eint2 external interrupt 2 arb0 eint1 external interrupt 1 arb0 eint0 external interrupt 0 arb0
interrupt controller s3c2400 risc micr oprocessor 14- 4 interrupt priority generating block the priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in the following figure. arbiter6 arbiter0 arm irq req1/eint0 arbiter1 arbiter2 arbiter3 arbiter4 arbiter5 req4/int_tick req5/int_wdt req0/int_timer0 req3/int_timer3 req2/int_timer2 req1/int_timer1 req4/int_timer4 req0/reserved req1/int_dma0 req3/int_dma2 req2/int_dma1 req5/int_uerr0/1 req4/int_dma3 req5/int_mmc req0/int_spi req1/int_urxd0 req2/int_urxd1 req3/int_usbd req4/int_usbh req5/int_iic req1/int_utxd0 req2/int_utxd1 req3/int_rtc req4/int_adc req0 req1 req2 req3 req4 req5 req2/eint1 req3/eint2 req4/eint3 req0/eint4 req1/eint5 req2/eint6 req3/eint7 figure 14-1. priority generating block
s3c2400 risc microprocessor interrupt controller 14- 5 interrupt priority each arbiter can handle six interrupt requests based on the one bit arbiter mode control(arb_mode) and two bits of selection control signals(arb_sel) as follows: if arb_sel bits are 00b, the priority order is req0, req1, req2, req3, req4, and req5. if arb_sel bits are 01b, the priority order is req0, req2, req3, req4, req1, and req5. if arb_sel bits are 10b, the priority order is req0, req3, req4, req1, req2, and req5. if arb_sel bits are 11b, the priority order is req0, req4, req1, req2, req3, and req5. note that req0 of an arbiter is always the highest priority, and req5 is the lowest one. in addition, by changing the arb_sel bits, we can rotate the priority of req1 - req4. here, if arb_mode bit is set to 0, arb_sel bits are not automatically changed, thus the arbiter operates in the fixed priority mode. (note that even in this mode, we can change the priority by manually changing the arb_sel bits.). on the other hand, if arb_mode bit is 1, arb_sel bits are changed in rotation fashion, e.g., if req1 is serviced, arb_sel bits are changed to 01b automatically so as to make req1 the lowest priority one. the detailed rule of arb_sel change is as follows. if req0 or req5 is serviced, arb_sel bits are not changed at all. if req1 is serviced, arb_sel bits are changed to 01b. if req2 is serviced, arb_sel bits are changed to 10b. if req3 is serviced, arb_sel bits are changed to 11b. if req4 is serviced, arb_sel bits are changed to 00b.
interrupt controller s3c2400 risc micr oprocessor 14- 6 interrupt controller special registers there are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. all the interrupt requests from the interrupt sources are first registered in the source pending register. they are divided into two groups based on the interrupt mode register, i.e., one fiq request and the remaining irq requests. arbitration process is performed for the multiple irq requests based on the priority register. source pending register (srcpnd) srcpnd register is composed of 32 bits each of which is related to an interrupt source. each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. by reading this register, we can see the interrupt sources waiting for their requests to be serviced. note that each bit of srcpnd register is automatically set by the interrupt sources regardless of the masking bits in the intmask register. in addition, it is not affected by the priority logic of interrupt controller. in the interrupt service routine for a specific interrupt source, the corresponding bit of srcpnd register has to be cleared to get the interrupt request from the same source correctly. if you return from the isr without clearing the bit, interrupt controller operates as if another interrupt request comes in from the same source. in other words, if a specific bit of srcpnd register is set to 1, it is always considered as a valid interrupt request waiting to be serviced. the specific time to clear the corresponding bit depends on the user's requirement. the bottom line is that if you want to receive another valid request from the same source you should clear the corresponding bit first, and then enable the interrupt. you can clear a specific bit of srcpnd register by writing a data to this register. it clears only the bit positions of srcpnd corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the data remains as they are with no change register address r/w description reset value srcpnd 0x14400000 r/w indicates the interrupt request status. 0 = the interrupt has not been requested. 1 = the interrupt source has asserted the interrupt request. 0x00000000 note : when the user clear a interrupt pending, specific bit of srcpnd and intpnd, has to clear the bit of srcpnd.
s3c2400 risc microprocessor interrupt controller 14- 7 srcpnd bit description initial state int_adc [31] 0 = not requested, 1 = requested 0 int_rtc [30] 0 = not requested, 1 = requested 0 int_utxd1 [29] 0 = not requested, 1 = requested 0 int_utxd0 [28] 0 = not requested, 1 = requested 0 int_iic [27] 0 = not requested, 1 = requested 0 int_usbh [26] 0 = not requested, 1 = requested 0 int_usbd [25] 0 = not requested, 1 = requested 0 int_urxd1 [24] 0 = not requested, 1 = requested 0 int_urxd0 [23] 0 = not requested, 1 = requested 0 int_spi [22] 0 = not requested, 1 = requested 0 int_mmc [21] 0 = not requested, 1 = requested 0 int_dma3 [20] 0 = not requested, 1 = requested 0 int_dma2 [19] 0 = not requested, 1 = requested 0 int_dma1 [18] 0 = not requested, 1 = requested 0 int_dma0 [17] 0 = not requested, 1 = requested 0 reserved [16] not used 0 int_uerr0/1 [15] 0 = not requested, 1 = requested 0 int_timer4 [14] 0 = not requested, 1 = requested 0 int_timer3 [13] 0 = not requested, 1 = requested 0 int_timer2 [12] 0 = not requested, 1 = requested 0 int_timer1 [11] 0 = not requested, 1 = requested 0 int_timer0 [10] 0 = not requested, 1 = requested 0 int_wdt [9] 0 = not requested, 1 = requested 0 int_tick [8] 0 = not requested, 1 = requested 0 eint7 [7] 0 = not requested, 1 = requested 0 eint6 [6] 0 = not requested, 1 = requested 0 eint5 [5] 0 = not requested, 1 = requested 0 eint4 [4] 0 = not requested, 1 = requested 0 eint3 [3] 0 = not requested, 1 = requested 0 eint2 [2] 0 = not requested, 1 = requested 0 eint1 [1] 0 = not requested, 1 = requested 0 eint0 [0] 0 = not requested, 1 = requested 0 .
interrupt controller s3c2400 risc micr oprocessor 14- 8 interrupt mode register (intmod) this register is composed of 32 bits each of which is related to an interrupt source. if a specific bit is set to 1, the corresponding interrupt is processed in the fiq (fast interrupt) mode. otherwise, it is processed in the irq mode (normal interrupt). note that at most only one interrupt source can be serviced in the fiq mode in the interrupt controller. (you should use the fiq mode only for the urgent interrupt.) thus, only one bit of intmod can be set to 1 at most. this register is write-only one, thus it cannot be read out. register address r/w description reset value intmod 0x14400004 w interrupt mode register. 0 = irq mode 1 = fiq mode 0x00000000 note : if an interrupt mode is set to fiq mode in intmod register, fiq interrupt will not affect intpnd and intoffset registers. the intpnd and intoffset registers are valid only for irq mode interrupt source.
s3c2400 risc microprocessor interrupt controller 14- 9 intmod bit description initial state int_adc [31] 0 = irq, 1 = fiq 0 int_rtc [30] 0 = irq, 1 = fiq 0 int_utxd1 [29] 0 = irq, 1 = fiq 0 int_utxd0 [28] 0 = irq, 1 = fiq 0 int_iic [27] 0 = irq, 1 = fiq 0 int_usbh [26] 0 = irq, 1 = fiq 0 int_usbd [25] 0 = irq, 1 = fiq 0 int_urxd1 [24] 0 = irq, 1 = fiq 0 int_urxd0 [23] 0 = irq, 1 = fiq 0 int_spi [22] 0 = irq, 1 = fiq 0 int_mmc [21] 0 = irq, 1 = fiq 0 int_dma3 [20] 0 = irq, 1 = fiq 0 int_dma2 [19] 0 = irq, 1 = fiq 0 int_dma1 [18] 0 = irq, 1 = fiq 0 int_dma0 [17] 0 = irq, 1 = fiq 0 reserved [16] not used 0 int_uerr0/1 [15] 0 = irq, 1 = fiq 0 int_timer4 [14] 0 = irq, 1 = fiq 0 int_timer3 [13] 0 = irq, 1 = fiq 0 int_timer2 [12] 0 = irq, 1 = fiq 0 int_timer1 [11] 0 = irq, 1 = fiq 0 int_timer0 [10] 0 = irq, 1 = fiq 0 int_wdt [9] 0 = irq, 1 = fiq 0 int_tick [8] 0 = irq, 1 = fiq 0 eint7 [7] 0 = irq, 1 = fiq 0 eint6 [6] 0 = irq, 1 = fiq 0 eint5 [5] 0 = irq, 1 = fiq 0 eint4 [4] 0 = irq, 1 = fiq 0 eint3 [3] 0 = irq, 1 = fiq 0 eint2 [2] 0 = irq, 1 = fiq 0 eint1 [1] 0 = irq, 1 = fiq 0 eint0 [0] 0 = irq, 1 = fiq 0
interrupt controller s3c2400 risc micr oprocessor 14- 10 interrupt mask register (intmsk) each of the 32 bits in the interrupt mask register is related to an interrupt source. if you set a specific bit to 1, the interrupt request from the corresponding interrupt source is not serviced by the cpu. (note that even in such a case, the corresponding bit of srcpnd register is set to 1). if the mask bit is 0, the interrupt request can be serviced. register address r/w description reset value intmsk 0x14400008 r/w determines which interrupt source is masked. the masked interrupt source will not be serviced. 0 = interrupt service is available 1 = interrupt service is masked 0xffffffff
s3c2400 risc microprocessor interrupt controller 14- 11 intmsk bit description initial state int_adc [31] 0 = service available, 1 = masked 1 int_rtc [30] 0 = service available, 1 = masked 1 int_utxd1 [29] 0 = service available, 1 = masked 1 int_utxd0 [28] 0 = service available, 1 = masked 1 int_iic [27] 0 = service available, 1 = masked 1 int_usbh [26] 0 = service available, 1 = masked 1 int_usbd [25] 0 = service available, 1 = masked 1 int_urxd1 [24] 0 = service available, 1 = masked 1 int_urxd0 [23] 0 = service available, 1 = masked 1 int_spi [22] 0 = service available, 1 = masked 1 int_mmc [21] 0 = service available, 1 = masked 1 int_dma3 [20] 0 = service available, 1 = masked 1 int_dma2 [19] 0 = service available, 1 = masked 1 int_dma1 [18] 0 = service available, 1 = masked 1 int_dma0 [17] 0 = service available, 1 = masked 1 reserved [16] not used 1 int_uerr0/1 [15] 0 = service available, 1 = masked 1 int_timer4 [14] 0 = service available, 1 = masked 1 int_timer3 [13] 0 = service available, 1 = masked 1 int_timer2 [12] 0 = service available, 1 = masked 1 int_timer1 [11] 0 = service available, 1 = masked 1 int_timer0 [10] 0 = service available, 1 = masked 1 int_wdt [9] 0 = service available, 1 = masked 1 int_tick [8] 0 = service available, 1 = masked 1 eint7 [7] 0 = service available, 1 = masked 1 eint6 [6] 0 = service available, 1 = masked 1 eint5 [5] 0 = service available, 1 = masked 1 eint4 [4] 0 = service available, 1 = masked 1 eint3 [3] 0 = service available, 1 = masked 1 eint2 [2] 0 = service available, 1 = masked 1 eint1 [1] 0 = service available, 1 = masked 1 eint0 [0] 0 = service available, 1 = masked 1
interrupt controller s3c2400 risc micr oprocessor 14- 12 priority register (priority) register address r/w description reset value priority 0x1440000c w irq priority control register 0x7f priority bit description initial state arb_sel6 [20:19] arbiter 6 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel5 [18:17] arbiter 5 group priority order set 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 0 arb_sel4 [16:15] arbiter 4 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel3 [14:13] arbiter 3 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel2 [12:11] arbiter 2 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel1 [10:9] arbiter 1 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel0 [8:7] arbiter 0 group priority order set 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 0 arb_mode6 [6] arbiter 6 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode5 [5] arbiter 5 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode4 [4] arbiter 4 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode3 [3] arbiter 3 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode2 [2] arbiter 2 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode1 [1] arbiter 1 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode0 [0] arbiter 0 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1
s3c2400 risc microprocessor interrupt controller 14- 13 interrupt pending register (intpnd) each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request is the highest priority one that is unmasked and waits for the interrupt to be serviced. since intpnd is located after the priority logic, only one bit can be set to 1 at most, and that is the very interrupt request generating irq to cpu. in interrupt service routine for irq, you can read this register to determine the interrupt source to be serviced among 32 sources. like the srcpnd, this register has to be cleared in the interrupt service routine after clearing srcpnd register. we can clear a specific bit of intpnd register by writing a data to this register. it clears only the bit positions of intpnd corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the data remains as they are with no change. register address r/w description reset value intpnd 0x14400010 r/w indicates the interrupt request status. 0 = the interrupt has not been requested 1 = the interrupt source has asserted the interrupt request 0x00000000 note : if the fiq mode interrupt is occurred, the corresponding bit of intpnd will not be turned on. because the intpnd register is available only for irq mode interrupt.
s3c2400 risc microprocessor interrupt controller 14- 14 intpnd bit description initial state int_adc [31] 0 = not requested, 1 = requested 0 int_rtc [30] 0 = not requested, 1 = requested 0 int_utxd1 [29] 0 = not requested, 1 = requested 0 int_utxd0 [28] 0 = not requested, 1 = requested 0 int_iic [27] 0 = not requested, 1 = requested 0 int_usbh [26] 0 = not requested, 1 = requested 0 int_usbd [25] 0 = not requested, 1 = requested 0 int_urxd1 [24] 0 = not requested, 1 = requested 0 int_urxd0 [23] 0 = not requested, 1 = requested 0 int_spi [22] 0 = not requested, 1 = requested 0 int_mmc [21] 0 = not requested, 1 = requested 0 int_dma3 [20] 0 = not requested, 1 = requested 0 int_dma2 [19] 0 = not requested, 1 = requested 0 int_dma1 [18] 0 = not requested, 1 = requested 0 int_dma0 [17] 0 = not requested, 1 = requested 0 reserved [16] not used 0 int_uerr0/1 [15] 0 = not requested, 1 = requested 0 int_timer4 [14] 0 = not requested, 1 = requested 0 int_timer3 [13] 0 = not requested, 1 = requested 0 int_timer2 [12] 0 = not requested, 1 = requested 0 int_timer1 [11] 0 = not requested, 1 = requested 0 int_timer0 [10] 0 = not requested, 1 = requested 0 int_wdt [9] 0 = not requested, 1 = requested 0 int_tick [8] 0 = not requested, 1 = requested 0 eint7 [7] 0 = not requested, 1 = requested 0 eint6 [6] 0 = not requested, 1 = requested 0 eint5 [5] 0 = not requested, 1 = requested 0 eint4 [4] 0 = not requested, 1 = requested 0 eint3 [3] 0 = not requested, 1 = requested 0 eint2 [2] 0 = not requested, 1 = requested 0 eint1 [1] 0 = not requested, 1 = requested 0 eint0 [0] 0 = not requested, 1 = requested 0
s3c2400 risc microprocessor interrupt controller 14- 15 interrupt offset register (intoffset) the number in the interrupt offset register shows which interrupt request of irq mode is in the intpnd register. this bit can be cleared automatically by clearing srcpnd and intpnd. register address r/w description reset value intoffset 0x14400014 r indicates the irq interrupt request source 0x00000000 int source the offset value int source the offset value int_adc 31 int_uerr0/1 15 int_rtc 30 int_timer4 14 int_utxd1 29 int_timer3 13 int_utxd0 28 int_timer2 12 int_iic 27 int_timer1 11 int_usbh 26 int_timer0 10 int_usbd 25 int_wdt 9 int_urxd1 24 int_tick 8 int_urxd0 23 eint7 7 int_spi 22 eint6 6 int_mmc 21 eint5 5 int_dma3 20 eint4 4 int_dma2 19 eint3 3 int_dma1 18 eint2 2 int_dma0 17 eint1 1 reserved 16 eint0 0 note : if the fiq mode interrupt is occurred, the intoffset will not be affected. because the intoffset register is ava ilable only for irq mode interrupt.
interrupt controller s3c2400 risc micr oprocessor 14- 16 notes
s3c2400 risc microprocessor lcd cont roller 15- 1 15 lcd controller overview the lcd controller within s3c2400 x01 consists of logic for transferring lcd image data from a video buffer located in system memory to an external lcd driver. the lcd controller supports monochrome, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a monochrome lcd, using a time-based dithering algorithm and frc (frame rate control) method and it can be interfaced with a color lcd panel at 8-bit per pixel (256-level color) and 12-bit per pixel (4096-level color) for interfacing with stn lcd. it can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, 8-bit per pixel for interfacing with the palettized tft color lcd panel and 16 non- palettized true-color display. the lcd controller can be programmed to support the different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate. features stn lcd displays features ? supports 3 types of lcd panels: 4-bit dual scan, 4-bit single scan, 8-bit single scan display type. ? supports the monochrome, 4 gray levels, and 16 gray levels . ? supports 256 level colors and 4096 level colors for color stn lcd panel. ? supports multiple screen size. typical actual screen sizes: 320 240, 160 160 (pixels) maximum virtual screen sizes(color mode): 4096 1024, 2048 2048, 1024 4096, etc tft lcd displays features ? supports 1, 2, 4 or 8 bpp (bit per pixel) palettized color displays for tft. ? supports 16 non- palettized true-color displays for color tft. ? supports maximum 64k color tft at 16-bit per pixel mode. ? supports multiple screen size. typical actual screen size: 720 240, 320 240, 160 160 (pixels) maximum virtual screen size (16 bpp mode): 2048 1024 etc
lcd controller s3 c2400 risc microprocessor 15- 2 common features ? dedicated dma supports to fetch the image data from video buffer located in system memory. ? supports power saving mode. ? the system memory is used as the display memory. ? supports multiple virtual display screen. (supports hardware hor izontal/vertical scrolling) ? programmable timing control for different display panels. ? supports little and big- endian byte ordering, as well as wince data formats. external interface signal vframe / vsync: frame synchronous signal (stn) / vertical sync hronous signal (tft). vline / hsync: line synchronous pulse signal (stn) / horizontal synchronous signal (tft) vclk: pixel clock signal (stn/tft) vd[15:0]: lcd pixel data output ports (stn/tft) vm / vden: ac bias signal for the stn lcd driv er (stn) / data enable signal (tft) lend: line end signal (tft) total 21 output ports, data 16 bits, control 5 bits
s3c2400 risc microprocessor lcd cont roller 15- 3 block diagram regbank system bus lcdcdma timegen vidprcs vd[15:0] vclk vline vframe vm . . . . figure 15-1. lcd controller block diagram the lcd controller within s3c2400 is used to transfer the video data and to generate the necessary control signals such as, vframe, vline, vclk, vm and so on. as well as the control signals, s3c2400has the data ports of video data, which are vd[15:0] as shown in figure 15-1. the lcd controller consists of a regbank, lcdcdma, vidprcs, and timegen (see figure 15-1 lcd controller block diagram). the regbank has 21 programmable register sets and 256x16 palette memory which are used to configure the lcd controller. the lcdcdma is a dedicated dma, which it can transfer the video data in frame memory to lcd driver, automatically. by using this special dma, the video data can be displayed on the screen without cpu intervention. the vidprcs receives the video data from lcdcdma and sends the video data through the vd[15:0] data ports to the lcd driver after changing them into a suitable data format, for example 4/8-bit single scan or 4-bit dual scan display mode. the timegen consists of programmable logic to support the variable requirement of interface timing and rates commonly found in different lcd drivers. the timegen block generates vframe, vline, vclk, vm, and so on. the description of data flow is as follows: fifo memory is present in the lcdcdma. when fifo is empty or partially empty, lcdcdma requests data fetching from the frame memory based on the burst memory transfer mode(consecutive memory fetching of 4 words(16 bytes) per one burst request without allowing the bus mastership to another bus master during the bus transfer). when this kind of transfer request is accepted by bus arbitrator in the memory controller, there will be four successive word data transfers from system memory to internal fifo. the total size of fifo is 24 words, which consists of fifol and fifoh of 12 words, respectively. the s3c2400 has two fifos because it needs to support the dual scan display mode. in case of single scan mode, one of them can only be used.
lcd controller s3 c2400 risc microprocessor 15- 4 lcd controller operation (stn case) timing generator the timegen generates the control signals for lcd driver such as, vframe, vline, vclk, and vm. these control signals are closely related to the configuration on the lcdcon1/2/3/4/5 register in the regbank. based on these programmable configurations on the lcd control registers in regbank, the timegen can generate the programmable control signals suitable to support many different types of lcd drivers. the vframe pulse is asserted for a duration of the entire first line at a frequency of once per frame. the vframe signal is asserted to bring the lcd's line pointer to the top of the display to start over. the vm signal is used by the lcd driver to alternate the polarity of the row and column voltage used to turn the pixel on and off. the toggle rate of vm signal can be controlled by using the mmode bit of lcdcon 1 register and mval field of lcdcon4 register. if the mmode bit is 0, the vm signal is configured to toggle on every frame. if the mmode bit is 1, the vm signal is configured to toggle on the every event of the elapse of the specified number of vline by the mval[7:0] value. figure 15-5 shows an example for mmode=0 and for mmode=1 with the value of mval[7:0]=0x2. when mmode=1, the vm rate is related to mval[7:0], as shown below: vm rate = vline rate / ( 2 mval) the vframe and vline pulse generation is controlled by the configurations of the hozval field and the lineval field in the lcdcon2/3 register. each field is related to the lcd size and display mode. in other words, the hozval and lineval can be determined by the size of the lcd panel and the display mode according to the following equation: hozval = (horizontal display size / number of the valid vd data line) -1 in color mode: horizontal display size = 3 number of horizontal pixel in the 4-bit single scan display mode, number of valid vd data lines should be 4. in case of 4-bit dual scan display the number of valid vd data lines should be 4 and in case of 8-bit single scan display mode, the number of valid vd data lines should be 8. lineval = (vertical display size) -1 : in case of single scan display type lineval = (vertical display size / 2) -1 : in case of dual scan display type the rate of vclk signal can be controlled by the clkval field in the lcdcon1 register. the table 15-1 defines the relationship of vclk and clkval. the minimum value of clkval is 2. vclk( hz)=hclk/(clkval x 2) the frame rate is the vfram signal frequency. the frame rate is closely related to the field of wlh[1:0](vline pulse width) wdly[1:0](the delay width of vclk after vline pulse), hozval, lineblank, and lineval in lcdcon1 and lcdcon2/3/4 registers as well as vclk and hclk. most lcd drivers need their own adequate frame rate. the frame rate is calculated as follows; frame_rate(hz) = 1 / [((1/vclk) x (hozval+1)+(1/hclk) x (wlh+wdly+(lineblank x 8) ) ) x (lineval+1)] vclk(hz) = (hozval+1 ) / [(1 /( frame_rate x (lineval+1))) - ((wlh+wdly+(lineblank x 8) ) / hclk )]
s3c2400 risc microprocessor lcd cont roller 15- 5 table 15-1. relation between vclk and clkval(stn, hclk=60mhz) clkval 60mhz/x vclk 2 60 mhz/4 15.0 mhz 3 60 mhz/6 10.0 mhz 1023 60 mhz/2046 29.3 khz video operation the lcd controller within s3c2400 supports 8-bit color mode (256 color mode), 12-bit color mode (4096 color mode), 4 level gray scale mode, 16 level gray scale mode as well as the monochrome mode. when the gray or color mode is needed, the implementation of the shades of gray level or color should be followed by time-based dithering algorithm and frc(frame rate control) method can be used to implement the shades of gray or color from which selection can be made by using a programmable lockup table, which will be explained later. the monochrome mode bypasses these modules(frc and lookup table) and basically serializes the data in fifoh (and fifol if a dual scan display type is used) into 4-bit (or 8-bit if a 4-bit dual scan or 8-bit single scan display type is used) streams by shifting the video data to the lcd driver. the following sections describe the operation on gray mode and color mode in terms of the lookup table and frc. lookup table the s3c2400 can support the palette table for various selection of color or gray level mapping. this kind of selection gives users flexibility. the lookup table is the palette which allows the selection on the level of color or gray(selection on 4-gray levels among 16 gray levels in case of gray mode, selection on 8 red levels among 16 levels, 8 green levels among 16 levels and 4 blue levels among 16 levels in case of color mode). in other words, users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode. the gray levels cannot be selected in the 16 gray level mode; all 16 gray levels must be chosen among the possible 16 gray levels. in case of 256 color mode, 3 bits are allocated for red, 3 bits for green and 2 bits for blue. the 256 colors mean that the colors are formed from the combination of 8 red, 8 green and 4 blue levels(8x8x4 = 256). in the color mode, the lookup table can be used for suitable selections. eight red levels can be selected among 16 possible red levels, 8 green levels among 16 green levels, and 4 blue levels among 16 blue levels. in case of 4096 color mode, of course there is no selection as in the 256 color mode. gray mode operation two gray modes are supported by the lcd controller within the s3c2400: 2-bit per pixel gray (4 level gray scale) or 4-bit per pixel gray (16 level gray scale). the 2-bit per pixel gray mode uses a lookup table, which allows selection on 4 gray levels among 16 possible gray levels. the 2-bit per pixel gray lookup table uses the buleval[15:0] in bluelut(blue lookup table) register as same as blue lookup table in color mode. the gray level 0 will be denoted by blueval[3:0] value. if blueval[3:0] is 9, level 0 will be represented by gray level 9 among 16 gray levels. if blueval[3:0] is 15, level 0 will be represented by gray level 15 among 16 gray levels, and so on. as same as in the case of level 0, level 1 will also be denoted by blueval[7:4], the level 2 by blueval[11:8], and the level 3 by blueval[15:12]. these four groups among blueval[15:0] will represent level 0, level 1, level 2, and level 3. in 16 gray levels, of course there is no selection as in the 4 gray levels.
lcd controller s3 c2400 risc microprocessor 15- 6 256 level color mode operation the lcd controller in s3c2400 can support an 8-bit per pixel 256 color display mode. the color display mode can generate 256 levels of color using the dithering algorithm and frc. the 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue. the color display mode uses separate lookup tables for red, green, and blue. each lookup table uses the redval[31:0] of redlut register, greenval[31:0] of greenlut register, and blueval[15:0] of bluelut register as the programmable lookup table entries. similarly with the gray level display, 8 group or field of 4 bits in the redlur register, i.e., redval[31:28], redlut[27:24], redlut[23:20], redlut[19:16], redlut[15:12], redlut[11:8], redlut[7:4], and redlut[3:0], are assigned to each red level. the possible combination of 4 bits(each field) is 16, and each red level should be assigned to one level among possible 16 cases. in other words, the user can select the suitable red level by using this type of lookup table. for green color, the greenval[31:0] of the greenlut register is assigned as the lookup table, as was done in the case of red color. similarly, the blueval[15:0] of the bluelut register is also assigned as a lookup table. for blue color, we need 16bit for a lookup table because 2 bits are allocated for 4 blue levels, different from the 8 red or green levels. 4096 level color mode operation the lcd controller in s3c2400can support an 12-bit per pixel 4096 color display mode. the color display mode can generate 4096 levels of color using the dithering algorithm and frc. the 12-bit per pixel are encoded into 4-bits for red, 4-bits for green, and 4-bits for blue. the color display mode does not use lookup tables.
s3c2400 risc microprocessor lcd cont roller 15- 7 dithering and frc (frame rate control) for stn lcd displays(except monochrome), video data must be processed by a dithering algorithm. the dithfrc block has two functions, such as a time-based dithering algorithm for reducing flicker and frc(frame rate control) for displaying gray and color level on the stn panel. the main principle of gray and color level display on the stn panel based on frc is described. for example, to display the third gray (3/16) level from a total of 16 levels, the 3 times pixel should be on and 13 times pixel off. in other words, 3 frames should be selected among the 16 frames, of which 3 frames should have a pixel-on on a specific pixel while the remaining 13 frames should have a pixel-off on a specific pixel. these 16 frames should be displayed periodically. this is basic principle on how to display the gray level on the screen, so-called gray level display by frc(frame rate control). the actual example is shown in table 15-2. to represent the 14 th gray level in the table, we should have a 6/7 duty cycle, which mean that there are 6 times pixel-on and one time pixel-off. the other cases for all gray levels are also shown in table 15-2. in the stn lcd display, we should be reminded of one item, i.e., flicker noise due to the simultaneous pixel-on and -off on adjacent frames. for example, if all pixels on first frame are turned on and all pixels on next frame are turned off, the flicker noise will be maximized. to reduce the flicker noise on the screen, the average probability of pixel- on and -off between frames should be as same as possible. in order to realize this, the time-based dithering algorithm, which varies the pattern of adjacent pixels on every frame, should be used. this is explained in detail. for the 16 gray level, frc should have the following relationship between gray level and frc. the 15 th gray level should always have pixel-on, and the 14 th gray level should have 6 times pixel-on and one times pixel-off, and the 13 th gray level should have 4 times pixel-on and one times pixel-off, ,,,,,,,, , and the 0 th gray level should always have pixel-off as shown in table 15-2. table 15-2. dither duty cycle examples pre-dithered data (gray level number) duty cycle pre-dithered data (gray level number) duty cycle 15 1 7 1/2 14 6/7 6 3/7 13 4/5 5 2/5 12 3/4 4 1/3 11 5/7 3 1/4 10 2/3 2 1/5 9 3/5 1 1/7 8 4/7 0 0
lcd controller s3 c2400 risc microprocessor 15- 8 display types the lcd controller supports 3 types of lcd drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. figure 15-3 shows these 3 different display types for monochrome displays, and figure 15-4 show these 3 different display types for color displays. 4-bit dual scan display type a 4-bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time. the 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half, as shown in figure 15-3. the end of frame is reached when each half of the display has been shifted and transferred. the 8 pins (vd[7:0]) for the lcd output from the lcd controller can be directly connected to the lcd driver. 4-bit single scan display type a 4-bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. the 4 pins(vd[3:0]) for the lcd output from the lcd controller can be directly connected to the lcd driver, and the 4 pins(vd[7:4]) for the lcd output are not used. 8-bit single scan display type an 8-bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time, until the entire frame has been shifted and transferred. the 8 pins (vd[7:0]) for the lcd output from the lcd controller can be directly connected to the lcd driver. 256 color displays color displays require 3 bits (red, green, blue) of image data per pixel, resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line. this rgb is shifted to the lcd driver as consecutive bits via the parallel data lines. figure 15-4 shows the rgb and order of the pixels in the parallel data lines for the 3 types of color displays. 4096 color displays color displays require 3 bits (red, green, blue) of image data per pixel, resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line. this rgb is shifted to the lcd driver as consecutive bits via the parallel data lines. this rgb order is determined by the sequence of video data in video buffers.
s3c2400 risc microprocessor lcd cont roller 15- 9 memory data format (stn, bswp=0) mono 4-bit dual scan display: video buffer memory: address data 0000h a[31:0] 0004h b[31:0] 1000h l[31:0] 1004h m[31:0] mono 4-bit single scan display & 8-bit single scan display: video buffer memory: address data 0000h a[31:0] 0004h b[31:0] 0008h c[31:0] lcd panel lcd panel a[31] a[30] ...... a[0] b[31] b[30] ...... b[0] ...... l[31] l[30] ...... l[0] m[31] m[30] ...... m[0] ...... a[31] a[30] a[29] ...... a[0] b[31] b[30] ...... b[0] c[31] ...... c[0] ......
lcd controller s3 c2400 risc microprocessor 15- 10 in 4-level gray mode, 2 bits of video data correspond to 1 pixel. in 16-level gray mode, 4 bits of video data correspond to 1 pixel. in 256 level color mode, 8 bits (3 bits of red, 3 bits of green, 2 bits of blue) of video data correspond to 1 pixel. the color data format in a byte is as follows; bit [ 7:5 ] bit [ 4:2 ] bit[1:0] red green blue in 4096 level color mode, 12 bits (4 bits of red, 4 bits of green, 4 bits of blue) of video data correspond to 1 pixel. the color data format in words is as follows; ( video data must be reside at 3 word boundaries ( 8 pixel), as follows) rgb order data [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] word #1 red( 1) green(1) blue( 1) red( 2) green( 2) blue( 2) red(3) green(3) word #2 blue(3) red(4) green(4) blue(4) red(5) green(5) blue(5) red(6) word #3 green(6) blue(6) red(7) green(7) blue(7) red(8) green(8) blue(8)
s3c2400 risc microprocessor lcd cont roller 15- 11 lcd self refresh mode the lcd controller within S3C2400X01 can support the self refresh mode to reduce power comsumption. the self refresh mode can only be applied to only the lcd which has the special lcd driver, for example, lcd panel of sed1580d from seiko epson corporation. the sed1580d has the built-in monochrome display memory, which can display the previous stored image in the built-in monochrome display memory without image data fetch when the self refresh mode has been invoked. but sed1580d has the built-in display memory for monochrome only. so, the user has to set one more frame as a monochrome mode before the entering to self refresh mode. the kind of self refresh mode can be made by writing the control bit of selfref in the lcdcon5 register. if the selfref bit is set to 1, the lcd controller enters into the self refresh mode from the next line. when the lcd controller enters into the self refresh mode, the signal of vclk and vd should be fixed as low and last data value, but the signal of vm, vframe, and vline will be generated continuously. to exit the self refresh mode, the user should disable selfref bit in lcdcon 5 register. sl_idle mode (lcd dedicated idle mode) the sl_idle mode in the power management scheme should be used to enter into the lcd driver's self refresh mode. in sl_idle mode, all function blocks except the lcd controller within S3C2400X01should be stopped to reduce the power comsumption, because the power management block inserts divide_by_n input clock only to the lcd controller. for more information, please refer to the chapter, clock & power management and our example source code. timing requirements image data should be transferred from the memory to the lcd driver using the vd[7:0] signal. vclk signal is used to clock the data into the lcd driver's shift register. after each horizontal line of data has been shifted into the lcd driver's shift register, the vline signal is asserted to display the line on the panel. the vm signal provides an ac signal for the display. it is used by the lcd to alternate the polarity of the row and column voltages, used to turn the pixels on and off, because the lcd plasma tends to deteriorate whenever subjected to a dc voltage. it can be configured to toggle on every frame or to toggle every programmable number of vline signals. figure 15-5 shows the timing requirements for the lcd driver interface.
lcd controller s3 c2400 risc microprocessor 15- 12 4-bit dual scan display 4-bit single scan display 8-bit single scan display . . . . . . . . . . . . vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 vd3 vd2 vd1 vd0 . . . . . . vd7 vd6 vd5 vd4 vd3 vd2 vd1 vd0 . . . . . . figure 15-2. monochrome display types (stn)
s3c2400 risc microprocessor lcd cont roller 15- 13 vd3 r1 vd2 g1 vd1 b1 vd0 r2 vd3 g2 vd2 b2 vd1 r3 vd0 g3 . . . . . . 1 pixel . . . . . . 4-bit dual scan display vd3 r1 vd2 g1 vd1 b1 vd0 r2 vd3 g2 vd2 b2 vd1 r3 vd0 g3 . . . . . . 1 pixel 4-bit single scan display vd7 r1 vd6 g1 vd5 b1 vd4 r2 vd7 g2 vd6 b2 vd5 r3 vd4 g3 . . . . . . 1 pixel 8-bit single scan display vd7 r1 vd6 g1 vd5 b1 vd4 r2 vd3 g2 vd2 b2 vd1 r3 vd0 g3 figure 15-3. color display types (stn)
lcd controller s3 c2400 risc microprocessor 15- 14 vframe wdly vm vline wlh full frame timing, mmode = 0 line1 line2 line3 line4 line5 line6 line1 linen line1 line2 line3 line4 line5 line6 line1 linen first line timing linecnt decreases & display the 1st line lineblank first line check & data timing vframe vm vline vframe vm vline linecnt vclk vframe vm vline vclk vd[7:0] full frame timing, mmode = 1 wdly wdly display the last line of the previous frame figure 15-4. 8-bit single scan display type stn lcd timing
s3c2400 risc microprocessor lcd cont roller 15- 15 lcd controller operation(tft case) the timegen generates the control signals for lcd driver such as, vsync, hsync, vclk, vden, and lend signal. these control signals are highly related with the configuration on the lcdcon1/2/3/4/5 registers in the regbank. base on these programmable configuration on the lcd control registers in regbank, the timegen can generate the programmable control signals suitable for the support of many different types of lcd drivers. the vsync signal is asserted to cause the lcd's line pointer to start over at the top of the display. the vsync and hsync pulse generation is controlled by the configuration of both the hozval field and the lineval field in the lcdcon2/3 registers. the hozval and lineval can be determined by the size of the lcd panel according to the following equations: hozval = (horizontal display size) -1 lineval = (vertical display size) -1 the rate of vclk signal can be controlled by the clkval field in the lcdcon1 register. the table below defines the relationship of vclk and clkval. the minimum value of clkval is 1. vclk(hz)=hclk/[(clkval+1)x2] the frame rate is vsync signal frequency. the frame rate is related with the field of vsync, vbpd, vfpd, lineval, hsync, hbpd, hfpd, hozval, clkval in lcdcon1 and lcdcon2/3/4 registers. most lcd driver need their own adequate frame rate. the frame rate is calculated as follows; frame rate = 1/ [ { (vspw+1) + (vbpd+1) + (liineval + 1) + (vfpd+1) } x {(hspw+1) + (hbpd +1) + (hfpd+1) + (hozval + 1) } x { 2 x ( clkval+1 ) / ( system clk ) } ] table 15-3. relation between vclk and clkval(tft, hclk=60mhz) clkval 60mhz/x vclk 1 60 mhz/4 15.0 mhz 2 60 mhz/6 10.0 mhz : : : 1023 60 mhz/2048 30.0 khz video operation the tft lcd controller within S3C2400X01 supports 1, 2, 4 or 8 bpp(bit per pixel) palettized color displays and 16bpp non- palettized true-color displays. 256 color palette the S3C2400X01 can support the 256 color palette for various selection of color mapping. this kind of selection can give the flexibility to users
lcd controller s3 c2400 risc microprocessor 15- 16 memory data format (tft) bpp16 display (bswp = 0, hwswp = 0) d[31:16] d[15:0] 000h p1 p2 004h p3 p4 008h p5 p6 ... (bswp = 0, hwswp = 1) d[31:16] d[15:0] 000h p2 p1 004h p4 p3 008h p6 p5 ... p1 p2 p3 p4 p5 ...... lcd panel
s3c2400 risc microprocessor lcd cont roller 15- 17 bpp8 display (bswp = 0, hwswp = 0) d[31:24] d[23:16] d[15:8] d[7:0] 000h p1 p2 p3 p4 004h p5 p6 p7 p8 008h p9 p10 p11 p12 ... (bswp = 1, hwswp = 0) d[31:24] d[23:16] d[15:8] d[7:0] 000h p4 p3 p2 p1 004h p8 p7 p6 p5 008h p12 p11 p10 p9 ... p1 p2 p3 p4 p5 ...... lcd panel p6 p7 p8 p10 p11 p12 p9
lcd controller s3 c2400 risc microprocessor 15- 18 bpp4 display (bswp = 0, hwswp = 0) d[31:28] d[27:24] d[23:20] d[19:16] d[15:12] d[11:8] d[7:4] d[3:0] 000h p1 p2 p3 p4 p5 p6 p7 p8 004h p9 p10 p11 p12 p13 p14 p15 p16 008h p17 p18 p19 p20 p21 p22 p23 p24 ... (bswp = 1, hwswp = 0) d[31:28] d[27:24] d[23:20] d[19:16] d[15:12] d[11:8] d[7:4] d[3:0] 000h p7 p8 p5 p6 p3 p4 p1 p2 004h p15 p16 p13 p14 p11 p12 p9 p10 008h p23 p24 p21 p22 p19 p20 p17 p18 ... bpp2 display (bswp = 0, hwswp = 0) d [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] 000h p1 p2 p3 p4 p5 p6 p7 p8 004h p17 p18 p19 p20 p21 p22 p23 p24 008h p33 p34 p35 p36 p37 p38 p39 p40 ... d [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 000h p9 p10 p11 p12 p13 p14 p15 p16 004h p25 p26 p27 p28 p29 p30 p31 p32 008h p41 p42 p43 p44 p45 p46 p47 p48 ...
s3c2400 risc microprocessor lcd cont roller 15- 19 256 palette usage( tft ) palette configuration S3C2400X01 provides 256 color palette for tft lcd control. 256 color palette consist of the 256(depth) 16-bit spsram. palette supports 5:6:5(r:g:b) format and 5:5:5:1(r:g:b:i) format. when the user use 5:5:5:1 format, the intensity data(i) is used as a common lsb bit of each rgb data. so, 5:5:5:i format is same as r(5+i):g(5+i):b(5+i) format. for example, r(5+i)=vd[15:11]+vd[0], g(5+1)=vd[10:6]+vd[0], b(5+1)=vd[5:1]+vd[0]. the user can select 256 colors from the 64k colors through these two formats. table 15-4. 5:6:5 format index\bit pos. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address 00h r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 *0x14a00400 01h r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 0x14a00404 ....... ....... ffh r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 0x14a007fc table 15-5. 5:5:5:1 format index\bit pos. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address 00h r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 i 0x14a00400 01h r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 i 0x14a00404 ....... ....... ffh r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 i 0x14a007fc notes: 1. * 0x14a00400 is palette start address. 2. data[31:16] is invalid. palette read/write when the user going to do read/write operation on the palette, vstatus of lcdcon5 register must be checked. because read/write operation is prohibited during the active status of vstatus. temp configuration S3C2400X01 supports that the user can fill a frame with one color without complex modification to fill the one color to the video buffer or palette. the one colored frame can be displayed by the writing a value of the color which is displayed on lcd panel to tpalval of tpal register and enable tpalen. palette offset control the index of palette can be modified by the offset. this function provides special effect on lcd panel for the user.
lcd controller s3 c2400 risc microprocessor 15- 20 1 2 3 4 5 lcd panel 16bpp 5:5:5+1 format a[31] a[30] a[29] a[28] a[27] a[26]a[25] a[24] a[23] a[22] a[21] a[20] a[19]a[18] a[17] a[16] r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 r4 b3 b2 b1 b0 i 1 2 3 4 5 lcd panel 16bpp 5:6:5 format a[31] a[30] a[29] a[28] a[27] a[26]a[25] a[24] a[23] a[22] a[21] a[20] a[19]a[18] a[17] a[16] r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 figure 15-5. bpp16 5:6:5 display types (tft)
s3c2400 risc microprocessor lcd cont roller 15- 21 vsync hsync vden vspw+1 vbpd+1 vfpd+1 lineval+1 1 frame vden hspw+1 hbpd+1 hfpd+1 hozval+1 hsync vclk vd 1 line lend figure 15-6. tft lcd timing example
lcd controller s3 c2400 risc microprocessor 15- 22 virtual display (tft/stn) the S3C2400X01 supports hardware horizontal or vertical scrolling. if the screen is scrolled, the fields of lcdbaseu and lcdbasel in lcdsaddr1/2 registers need to be changed(refer to figure 15-8) but not the values of pagewidth and offsize. the size of video buffer in which the image is stored should be larger than lcd panel screen size. this is the data of line 1 of virtual screen. this is the data of line 1 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 11 of virtual screen. this is the data of line 11 of virtual screen. . . . before scrolling view port (the same size of lcd panel) lineval + 1 offsize pagewidth this is the data of line 1 of virtual screen. this is the data of line 1 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 11 of virtual screen. this is the data of line 11 of virtual screen. . . . after scrolling lcdbaseu lcdbasel offsize figure 15-7. example of scrolling in virtual display (single scan)
s3c2400 risc microprocessor lcd cont roller 15- 23 lcd controller special registers lcd control 1 register register address r/w description reset value lcdcon1 0x14a00000 r/w lcd control 1 register 0x00000000 lcdcon1 bit description initial state linecnt (read only) [27:18] these bits provide the status of the line counter. down count from lineval to 0 0000000000 clkval [17:8] these bits determine the rates of vclk and clkval[9:0]. stn : vclk = hclk / (clkval x 2) ( clkval 3 2 ) tft : vclk = hclk / [(clkval+1) x 2] ( clkval 3 1 ) 0000000000 mmode [7] this bit determines the toggle rate of the vm. 0 = each frame, 1 = the rate defined by the mval 0 pnrmode [6:5] these bits select the display mode. 00 = 4-bit dual scan display mode(stn) 01 = 4-bit single scan display mode(stn) 10 = 8-bit single scan display mode(stn) 11 = tft lcd panel 00 bppmode [4:1] these bits select the bpp ( bits per pixel) mode. 0000 = 1 bpp for stn, monochrome mode 0001 = 2 bpp for stn, 4-level gray mode 0010 = 4 bpp for stn, 16-level gray mode 0011 = 8 bpp for stn, color mode 0100 = 12 bpp for stn, color mode 1000 = 1 bpp for tft 1001 = 2 bpp for tft 1010 = 4 bpp for tft 1011 = 8 bpp for tft 1100 = 16 bpp for tft 0000 envid [0] lcd video output and the logic enable/disable. 0 = disable the video output and the lcd control signal. 1 = enable the video output and the lcd control signal. 0
lcd controller s3 c2400 risc microprocessor 15- 24 lcd control 2 register register address r/w description reset value lcdcon2 0x14a00004 r/w lcd control 2 register 0x00000000 lcdcon2 bit description initial state vbpd [31:24] tft : vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. stn : these bits should be set to zero on stn lcd. 0x00 lineval [23:14] tft/stn : these bits determine the vertical size of lcd panel. 0000000000 vfpd [13:6] tft : vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. stn : these bits should be set to zero on stn lcd. 00000000 vspw [5:0] tft : vertical sync pulse width determines the vsync pulse's high level width by counting the number of inactive lines. stn : these bits should be set to zero on stn lcd. 000000
s3c2400 risc microprocessor lcd cont roller 15- 25 lcd control 3 register register address r/w description reset value lcdcon3 0x14a00008 r/w lcd control 3 register 0x00000000 lcdcon3 bit description initial state hbpd (tft) [25:19] tft : horizontal back porch is the number of vclk periods between the falling edge of hsync and the start of active data. 0000000 wdly (stn) stn : wdly[1:0] bits determine the delay between vline and vclk by counting the number of the hclk. wdly[7:2] are reserved. 00 = 16clock, 01 = 32 clock, 10 = 64 clock, 11 = 128 clock hozval [18:8] tft/stn : these bits determine the horizontal size of lcd panel. hozval has to be determined to meet the condition that total bytes of 1 line are 2n bytes. if the x size of lcd is 120 dot in mono mode, x=120 can not be supported because 1 line is consist of 15 bytes. instead, x=128 in mono mode can be supported because 1 line is consisted of 16 bytes (2n). lcd panel driver will discard the additional 8 dot. 00000000000 hfpd (tft) [7:0] tft : horizontal front porch is the number of vclk periods between the end of active data and the rising edge of hsync. 0x00 lineblank (stn) stn : these bits indicate the blank time in one horizontal line duration time. these bits adjust the rate of the vline finely. the unit of lineblank is hclk x 8. ex) if the value of lineblank is 10, the blank time is inserted to vclk during 80 hclks.
lcd controller s3 c2400 risc microprocessor 15- 26 lcd control 4 register register address r/w description reset value lcdcon4 0x14a0000c r/w lcd control 4 register 0x00000000 lcdcon4 bit description initial state paladden [24] tft : palette index offset enable 0 = disable 1 = enable 0 addval [23:16] tft : palette index offset value 0x00 mval [15:8] stn : these bit define the rate at which the vm signal will toggle if the mmode bit is set logic '1'. 0x00 hspw(tft) [7:0] tft : horizontal sync pulse width determines the hsync pulse's high level width by counting the number of the vclk. 0x00 wlh(stn) stn : wlh[1:0] bits determine the vline pulse's high level width by counting the number of the hclk. wlh[7:2] are reserved. 00 = 16clock, 01 = 32 clock, 10 = 64 clock, 11 = 128 clock
s3c2400 risc microprocessor lcd cont roller 15- 27 lcd control 5 register register address r/w description reset value lcdcon5 0x14a00010 r/w lcd control 5 register 0x00000000 lcdcon5 bit description initial state vstatus [20:19] tft : vertical status (read only) 00 = vsync 01 = back porch 10 = active 11 = front porch 00 hstatus [18:17] tft : horizontal status (read only) 00 = hsync 01 = back porch 10 = active 11 = front porch 00 reserved [16] this bit is reserved and the value should be ? 0 ? . 0 reserved [15] this bit is reserved for test mode and the value should be ? 0 ? . 0 slowclksync [14] stn: if slowclksync is 1, the slow mode will be entered from normal mode synchronously when current lcd frame is completed. also, if slowclksync is 1, the normal mode will be entered from slow mode synchronously when current lcd frame is completed. this feature will be used for changing hclk and sl_idle mode. 0 = disable 1 = enable 0 selfref [13] stn : lcd self refresh mode enable bit 0 = lcd self refresh mode disable 1 = lcd self refresh mode enable 0 reserved [12] 0 reserved [11] 0 invvclk [10] stn/tft : this bit controls the polarity of the vclk active edge. 0 = the video data is fetched at vclk falling edge 1 = the video data is fetched at vclk rising edge 0 invvline [9] stn/tft : this bit indicates the vline/hsync pulse polarity. 0 = normal 1 = inverted 0 invvframe [8] stn/tft : this bit indicates the vframe/vsync pulse polarity. 0 = normal 1 = inverted 0 invvd [7] stn/tft : this bit indicates the vd (video data) pulse polarity. 0 = normal 1 = vd is inverted. 0
lcd controller s3 c2400 risc microprocessor 15- 28 lcd control 5 register (continued) lcdcon5 bit description initial state invvden [6] tft : this bit indicates the vden signal polarity. 0 = normal 1 = inverted 0 reserved [5] 0 invendline [4] tft : this bit indicates the lend signal polarity. 0 = normal 1 = inverted 0 reserved [3] 0 enlend [2] tft : lend output signal enable/disable. 0 = disable lend signal 1 = enable lend signal 0 bswp [1] stn/tft : byte swap control bit 0 = swap disable 1 = swap enable 0 hwswp [0] stn/tft : half-word swap control bit 0 = swap disable 1 = swap enable 0
s3c2400 risc microprocessor lcd cont roller 15- 29 frame buffer start address 1 register register address r/w description reset value lcdsaddr1 0x14a00014 r/w stn/tft : frame buffer start address 1 register 0x00000000 lcdsaddr1 bit description initial state lcdbank [27:21] these bits indicate a[28:22] of the bank location for the video buffer in the system memory. lcdbank value can not be changed even when moving the view port. lcd frame buffer should be inside aligned 4mb region, which ensures that lcdbank value will not be changed when moving the view port. so, using the malloc() function the care should be taken. 0x00 lcdbaseu [20:0] for dual-scan lcd: these bits indicate a[21:1] of the start address of the upper address counter, which is for the upper frame memory of dual scan lcd or the frame memory of single scan lcd. for single-scan lcd: these bits indicate a[21:1] of the start address of the lcd frame buffer. 0x000000 frame buffer start address 2 register register address r/w description reset value lcdsaddr2 0x14a00018 r/w stn/tft : frame buffer start address 2 register 0x00000000 lcdsaddr2 bit description initial state lcdbasel [20:0] for dual-scan lcd: these bits indicate a[21:1] of the start address of the lower address counter, which is used for the lower frame memory of dual scan lcd. for single scan lcd: these bits indicate a[21:1] of the end address of the lcd frame buffer. lcdbasel = ((the fame end address) >>1) + 1 = lcdbaseu + (pagewidth+offsize)x(lineval+1) 0x0000 note: users can change the lcdbaseu and lcdbasel values for scrolling while lcd controller is turned on. but, users must not change the lcdbaseu and lcdbasel registers at the end of frame by referring to the linecnt field in lcdcon1 register. because of the lcd fifo fetches the next frame data prior t o the change in the frame. so, if you change the frame, the pre-fetched fifo data will be obsolete and lcd controller will display the incorrect screen. to check the linecnt, interrutpt should be masked. if any interrupt is executed just after reading linecnt, the read linecnt value may be obsolete because of the execution time of isr(interrupt service routine).
lcd controller s3 c2400 risc microprocessor 15- 30 frame buffer start address 3 register register address r/w description reset value lcdsaddr3 0x14a0001c r/w stn/tft : virtual screen address set 0x00000000 lcdsaddr3 bit description initial state offsize [21:11] virtual screen offset size(the number of half words) this value defines the difference between the address of the last half word displayed on the previous lcd line and the address of the first half word to be displayed in the new lcd line. 00000000000 pagewidth [10:0] virtual screen page width(the number of half words) this value defines the width of the view port in the frame 000000000 note: the values of pagewidth and offsize must be changed when envid bit is 0. example 1. lcd panel = 320*240, 16gray, single scan frame start address = 0xc500000 offset dot number = 2048 dots ( 512 half words ) lineval = 240-1 = 0xef pagewidth = 320*4/16 = 0x50 offsize = 512 = 0x200 lcdbank = 0xc500000 >> 22 = 0x31 lcdbaseu = 0x100000 >> 1 = 0x80000 lcdbasel = 0x80000 + ( 0x50 + 0x200 ) * ( 0xef + 1 ) = 0xa2b00 example 2. lcd panel = 320*240, 16gray, dual scan frame start address = 0xc500000 offset dot number = 2048 dots ( 512 half words ) lineval = 120-1 = 0x77 pagewidth = 320*4/16 = 0x50 offsize = 512 = 0x200 lcdbank = 0xc500000 >> 22 = 0x31 lcdbaseu = 0x100000 >> 1 = 0x80000 lcdbasel = 0x80000 + ( 0x50 + 0x200 ) * ( 0x77 + 1 ) = 0x91580 example 3. lcd panel = 320*240, color, single scan frame start address = 0xc500000 offset dot number = 1024 dots ( 512 half words ) lineval = 240-1 = 0xef pagewidth = 320*8/16 = 0xa0 offsize = 512 = 0x200 lcdbank = 0xc500000 >> 22 = 0x31 lcdbaseu = 0x100000 >> 1 = 0x80000 lcdbasel = 0x80000 + ( 0xa0 + 0x200 ) * ( 0xef + 1 ) = 0xa7600
s3c2400 risc microprocessor lcd cont roller 15- 31 red lookup table register register address r/w description reset value redlut 0x14a00020 r/w stn :red lookup table register 0x00000000 redlut bit description initial state redval [31:0] these bits define which of the 16 shades each of the 8 possible red combinations will choose. 000 = redval[3:0], 001 = redval[7:4] 010 = redval[11:8], 011 = redval[15:12] 100 = redval[19:16], 101 = redval[23:20] 110 = redval[27:24], 111 = redval[31:28] 0x00000000 green lookup table register register address r/w description reset value greenlut 0x14a00024 r/w stn :green lookup table register 0x00000000 greenlut bit description initial state greenval [31:0] these bits define which of the 16 shades each of the 8 possible green combinations will choose. 000 = greenval[3:0], 001 = greenval[7:4] 010 = greenval[11:8], 011 = greenval[15:12] 100 = greenval[19:16], 101 = greenval[23:20] 110 = greenval[27:24], 111 = greenval[31:28] 0x00000000 blue lookup table register register address r/w description reset value bluelut 0x14a00028 r/w stn :blue lookup table register 0x0000 bulelut bit description initial state blueval [15:0] these bits define which of the 16 shades each of the 4 possible blue combinations will choose 00 = blueval[3:0], 01 = blueval[7:4] 10 = blueval[11:8], 11 = blueval[15:12] 0x0000 note: address from 0x14a0002c to 0x14a00048 should not be used. this area is reserved for test mode.
lcd controller s3 c2400 risc microprocessor 15- 32 dithering mode register register address r/w description reset value dithmode 0x14a0004c r/w stn :dithering mode register. this register reset value is 0x00000 but, user can change this value to 0x12210. ( please, refer to a sample program source for the latest value of this register ). 0x00000 dithmode bit description initial state dithmode [18:0] use one of following value for your lcd 0x00000 or 0x12210 0x00000
s3c2400 risc microprocessor lcd cont roller 15- 33 temp palette register register address r/w description reset value tpal 0x14a00050 r/w tft :temporary palette register. this register value will be video data at next frame 0x00000000 dithmode bit description initial state tpalen [16] temporary palette register enable bit 0 = disable 1 = enable 0 tpalval [15:0] temporary palette value register. 5:6:5 format: tpalval[15:11] : red tpalval[10:5] : green tpalval[4:0] : blue 5:5:5:1 format: tpalval[15:11] : red tpalval[10:6] : green tpalval[5:1] : blue tpalval[1] : intensity 0x000000
lcd controller s3 c2400 risc microprocessor 15- 34 register setting guide (stn) the maximum vclk frequency of the lcd controller is 16.5mhz whenever hclk frequency is 66 mhz; therefore the lcd controller supports all existing lcd drivers. the lcd controller supports multiple screen sizes by special register setting. the clkval value determines the frequency of vclk. the data transmission rate for the vd port of the lcd controller should be calculated, in order to determine the value of clkval register. the data transmission rate is given by the following equation: clkval has to be determined, such that the vclk value is greater than the data transmission rate. data transmission rate = hs vs fr mv hs: horizontal lcd size vs: vertical lcd size fr: frame rate mv: mode dependent value table 15-6. mv value for each display mode mode mv value mono, 4-bit single scan display 1/4 mono, 8-bit single scan display or 4-bit dual scan display 1/8 4 level gray, 4-bit single scan display 1/4 4 level gray, 8-bit single scan display or 4-bit dual scan display 1/8 16 level gray, 4-bit single scan display 1/4 16 level gray, 8-bit single scan display or 4-bit dual scan display 1/8 color, 4-bit single scan display 3/4 color, 8-bit single scan display or 4-bit dual scan display 3/8 the lcdbaseu register value is the first address value of the frame buffer. the lowest 4 bits must be eliminated for burst 4 word access. the lcdbasel register value is determined by lcd size and lcdbaseu. the lcdbasel value is given by the following equation: lcdbasel = lcdbaseu + lcdbasel offset
s3c2400 risc microprocessor lcd cont roller 15- 35 example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, hclk frequency is 60 mhz wlh = 1, wdly = 1. data transmission rate = 160 160 80 1/4 = 512 khz clkval = 58, vclk = 517khz hozval = 39, lineval = 159 lineblank =10 lcdbasel = lcdbaseu + 3200 note: the higher the system load is, the lower the cpu performance is. example 2 (virtual screen register): 4 -level gray, vertual screen size = 1024 x 1024, lcd size = 320 x 240, lcdbaseu = 0x64, 4-bit dual scan. 1 half-word = 8 pixels (4-level gray), virtual screen 1 line = 128 half-word = 1024 pixels, lcd 1 line = 320 pixels = 40 half-word, offsize = 128 - 40 = 88 = 0x58, pagewidth = 40 = 0x28 lcdbasel = lcdbaseu + (pagewidth + offsize) x (lineval +1) = 100 + (40 +88) x 120 = 0x3c64
lcd controller s3 c2400 risc microprocessor 15- 36 gray level selection guide S3C2400X01lcd controller can generate 16 gray level using frc(frame rate control). the frc characteristics may cause unexpected patterns in gray level. these unwanted erronous patterns may be shown in fast response lcd or at lower frame rates. because the quality of lcd gray levels depends on lcd's own characteristics, the user has to select the good gray levels after viewing all gray levels on user's own lcd. please select the gray level quality through the following procedures. 1. get the latest dithering pattern register value from samsung. 2. display 16gray bar in lcd. 3. change the frame rate into an optimal value. 4. change the vm alternating period to get the best quality. 5. as viewing 16 gray bars, select the good gray levels, which is displayed well on your lcd. 6. use only the good gray levels for quality. lcd refresh bus bandwidth calculation guide S3C2400X01lcd controller can supports various lcd display size. to select suitable lcd display size(for the flicker free lcd system application), the user have to consider the lcd refresh bus bandwidth determined by lcd display size, bit per pixel( bpp), frame rate, memory bus width, memory type and so on. lcd data rate(byte/s) = bpp x (horizontal display size) x (vertical display size) x (frame rate) /8 lcd dma burst count(times/s ) = lcd data rate(byte/s) /16(byte) ; lcd dma using 4words(16byte) burst pdma means lcd dma access period. in other words, the value of pdma is the period of four-beat burst(4-words burst) for video data fetch. so, pdma is determined by memory type and memory setting. eventually, lcd system load is determined by lcd dma burst count and pdma. lcd system load = lcd dma burst count x pdma example 3 : 640 x 480, 8bpp, 60 frame/sec, 16-bit data bus width, sdram(trp=2hclk / trcd=2hclk / cl=2hclk) and hclk frequency is 60 mhz lcd data rate = 8 640 480 60 / 8 = 18.432mbyte/s lcd dma burst count = 18.432 / 16 = 1.152m/s pdma = (trp+trcd+cl+(2 4)+1) (1/60mhz) = 0.250ms lcd system load = 1.152 250 = 0.288 system bus occupation rate = (0.288/1) 100 = 28.8%
s3c2400 risc microprocessor lcd cont roller 15- 37 register setting guide (tft lcd) the maximum vclk frequency of the tft lcd controller is 15 mhz whenever hclk frequency can use 60 mhz. for applications, the system timing must be considered to avoid under-run condition of the fifo of the lcd controller caused by memory bandwidth contention. the clkval register value determines the frequency of vclk and frame rate. frame rate = 1/ [ { (vspw+1) + (vbpd+1) + (liineval + 1) + (vfpd+1) } x {(hspw+1) + (hbpd +1) + (hfpd+1) + (hozval + 1) } x { 2 x ( clkval+1 ) / ( system clk ) } ] example 4 : tft resolution : 240 x 240, vspw =2 , vbpd =14, lineval = 239, vfpd =4 hspw =25, hbpd =15, hozval = 239, hfpd =1 clkval = 5 hclk = 60 m ( hz) below parameter must be referenced by lcd size, and driver specification: vspw, vbpd, lineval, vfpd, hspw, hbpd, hozval, hfpd if target frame rate is 60 ? 70hz then clkval should be 5. so, frame rate = 67hz
lcd controller s3 c2400 risc microprocessor 15- 38 notes
s3c2400 risc microprocessor a/d convert er 16- 1 16 a/d converter overview the 10-bit cmos adc (analog to digital converter) of s3c2400 is a recycling type device with 8-channel analog inputs. it converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500ksps with 2.5mhz a/d converter clock. a/d converter operates with on-chip sample-and-hold function and power down mode is supported. features ? resolution: 10-bit ? differential linearity error: 1.0 lsb ? integral linearity error: 2.0 lsb ? maximum conversion rate: 500 ksps ? low power consumption ? power supply voltage: 3.3v ? analog input range: 0 ? 3.3v ? on-chip sample-and-hold function
a/d converter s3c24 00 risc microprocessor 16- 2 a/d converter operation block diagram figure 16-1 shows the functional block diagram of s3c2400 a/d converter. note that the a/d converter device is a recycling type. pclk control logic psr ain[7:0] flash mdac mdac flash adcdat[11:0] eoc avref figure 16-1. a/d converter functional block diagram function descriptions a/d conversion time when the pclk frequency is 50mhz and the prescaler value is 49, total 10-bit conversion time is as follows. a/d converter freq. = 50mhz/(49+1) = 1mhz conversion time = 1/(1mhz / 5cycles) = 1/200khz = 5 us note: this a/d converter was designed to operate at maximum 2.5mhz clock, so the conversion rate can go up to 500 ksps. standby mode standby mode is activated when adccon[2] is set to '1'. in this mode, a/d conversion operation is halted and adcdat register contains the previous converted data.
s3c2400 risc microprocessor a/d convert er 16- 3 programming notes 1. the a/d converted data can be accessed by means of interrupt or polling method. with interrupt method the overall conversion time - from a/d converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time. with polling method, by checking the adccon[15] - end of conversion flag-bit, the read time from adcdat register can be determined. 2. another way for starting a/d conversion is provided. after adccon[1] - a/d conversion start-by-read mode-is set to 1, a/d conversion starts simultaneously whenever converted data is read.
a/d converter s3c24 00 risc microprocessor 16- 4 a/d converter special registers a/d converter control register (adccon) register address r/w description reset value adccon 0x15800000 r/w a/d converter control register 0x3fc4 adccon bit description initial state ecflg [15] reserved 0 prscen [14] a/d converter prescaler enable 0 = disable 1 = enable 0 prscvl [13:6] a/d converter prescaler value data value: 1 ? 255 note that division factor is (n+1) when prescaler value is n. 0xff input select [5:3] analog input channel select 000 = ain 0 001 = ain 1 010 = ain 2 011 = ain 3 100 = ain 4 101 = ain 5 110 = ain 6 111 = ain 7 0 stdbm [2] standby mode select 0 = normal operation mode 1 = standby mode 1 read _ start [1] a/d conversion start by read 0 = disable start by read operation 1 = enable start by read operation 0 enable _start [0] a/d conversion starts by writing ? 1 ? . write) 0 = no operation 1 = a/d conversion starts read) 0 = a/d conversion is completed. 1 = a/d conversion is being processed. 0
s3c2400 risc microprocessor a/d convert er 16- 5 a/d converter data register (adcdat) register address r/w description reset value adcdat 0x15800004 r a/d converter data register ? adcdat bit description initial state adcdat [9:0] a/d converter data value data value: 0 ? 3ff note that the converted data is loaded automatically after adccon[15] goes to 1. ?
a/d converter s3c24 00 risc microprocessor 16- 6 notes
s3c2400 risc microprocessor real time clock 17- 1 17 rtc (real time clock) overview the rtc (real time clock) unit can be operated by the backup battery while the system power is off. the rtc can transmit 8-bit data to cpu as bcd (binary coded decimal) values using the strb/ldrb arm operation. the data include second, minute, hour, date, day, month, and year. the rtc unit works with an external 32.768 khz crystal and also can perform the alarm function. feature ? bcd number: second, minute, hour, date, day, month, year ? leap year generator ? alarm function: alarm interrupt or wake-up from power down mode. ? year 2000 problem is removed. ? independent power pin (rtcvdd) ? supports millisecond tick time interrupt for rtos kernel time tick. ? round reset function
s3c2400 risc microprocessor real time clock 17- 2 real time clock operation 2 15 clock divider xtortc xtirtc control register sec min hour date day mon year leap year generator alarm generator reset register 1 hz rtccon rtcalm rtcrst time tick generator time tick ticnt 128 hz almint pmwkup pwdn figure 17-1. real time clock block diagram leap year generator this block can determine whether the last date of each month is 28, 29, 30, or 31, based on data from bcdday, bcdmon, and bcdyear. this block considers the leap year in deciding on the last date. an 8-bit counter can only represent 2 bcd digits, so it cannot decide whether 00 year is a leap year or not. for example, it can not discriminate between 1900 and 2000. to solve this problem, the rtc block in S3C2400X01 has hard-wired logic to support the leap year in 2000. please note 1900 is not leap year while 2000 is leap year. therefore, two digits of 00 in S3C2400X01 denote 2000, not 1900. read/write registers bit 0 of the rtccon register must be set to high in order to write the bcd register in rtc block. to display the sec., min., hour, date, month, and year, the cpu should read the data in bcdsec, bcdmin, bcdhour, bcdday, bcddate, bcdmon, and bcdyear registers, respectively, in the rtc block. however, a one second deviation may exist because multiple registers are read. for example, when the user reads the registers from bcdyear to bcdmin, the result is assumed to be 2059(year), 12(month), 31(date), 23(hour) and 59(minute). when the user read the bcdsec register and the result is a value from 1 to 59(second), there is no problem, but, if the result is 0 sec., the year, month, date, hour, and minute may be changed to 2060(year), 1(month), 1(date), 0(hour) and 0(minute) because of the one second deviation that was mentioned. in this case, user should re-read from bcdyear to bcdsec if bcdsec is zero. backup battery operation the rtc logic can be driven by the backup battery, which supplies the power through the rtcvdd pin into rtc block, even if the system power is off. when the system off, the interfaces of the cpu and rtc logic should be blocked, and the backup battery only drives the oscillation circuit and the bcd counters to minimize power dissipation.
s3c2400 risc microprocessor real time clock 17- 3 alarm function the rtc generates an alarm signal at a specified time in the power down mode or normal operation mode. in normal operation mode, the alarm interrupt (almint) is activated. in the power down mode the power management wakeup (pmwkup) signal is activated as well as the almint. the rtc alarm register, rtcalm, determines the alarm enable/disable and the condition of the alarm time setting. tick time interrupt the rtc tick time is used for interrupt request. the ticnt register has an interrupt enable bit and the count value for the interrupt. the count value reaches '0' when the tick time interrupt occurs. then the period of interrupt is as follow: period = ( n+1 ) / 128 second n: tick time count value (1 ? 127) this rtc time tick may be used for rtos(real time operating system) kernel time tick. if time tick is generated by rtc time tick, the time related function of rtos will always synchronized with real time. round reset function the round reset function can be performed by the rtc round reset register, rtcrst. the round boundary (30, 40, or 50 sec) of the second carry generation can be selected, and the second value is rounded to zero in the round reset. for example, when the current time is 23:37:47 and the round boundary is selected to 40 sec, the round reset changes the current time to 23:38:00. note all rtc registers have to be accessed by the byte unit using the strb,ldrb instructions or char type pointer. 32.768 khz x-tal connection example the figure 17-2 is an example circuit of the rtc unit oscillation at 32.768 khz. xtirtc xtortc 32768 hz 15 - 22pf figure 17-2. main oscillator circuit examples
s3c2400 risc microprocessor real time clock 17- 4 real time clock special registers real time clock control register (rtccon) the rtccon register consists of 4 bits such as the rtcen, which controls the read/write enable of the bcd registers, clksel, cntsel, and clkrst for testing. rtcen bit can control all interfaces between the cpu and the rtc, so it should be set to 1 in an rtc control routine to enable data read/write after a system reset. also before power off, the rtcen bit should be cleared to 0 to prevent inadvertent writing into rtc registers. register address r/w description reset value rtccon 0x15700040(l) 0x15700043(b) r/w (by byte) rtc control register 0x0 rtccon bit description initial state rtcen [0] rtc control enable 0 = disable 1 = enable note: only bcd time count and read operation can be performed. 0 clksel [1] bcd clock select 0 = xtal 1/2 15 divided clock 1 = reserved (xtal clock only for test) 0 cntsel [2] bcd count select 0 = merge bcd counters 1 = reserved (separate bcd counters) 0 clkrst [3] rtc clock count reset 0 = no reset, 1 = reset 0 notes: 1. all rtc registers have to be accessed by byte unit using strb and ldrb instructions or char type pointer. 2. (l): when the endian mode is little endian. (b): when the endian mode is big endian. tick time count register (ticnt) register address r/w description reset value ticnt 0x15700044(l) 0x15700047(b) r/w (by byte) tick time count register 0x00000000 ticnt bit description initial state tick int enable [7] tick time interrupt enable 0 = disable 1 = enable 0 tick time count [6:0] tick time count value. (1 ? 127) this counter value decreases internally, and users can not read this real counter value in working. 000000
s3c2400 risc microprocessor real time clock 17- 5 rtc alarm control register (rtcalm) rtcalm register determines the alarm enable and the alarm time. note that the rtcalm register generates the alarm signal through both almint and pmwkup in power down mode, but only through almint in the normal operation mode. register address r/w description reset value rtcalm 0x15700050(l) 0x15700053(b) r/w (by byte) rtc alarm control register 0x00 rtcalm bit description initial state reserved [7] reserved to 0. 0 almen [6] alarm global enable 0 = disable, 1 = enable 0 yearen [5] year alarm enable 0 = disable, 1 = enable 0 monren [4] month alarm enable 0 = disable, 1 = enable 0 dayen [3] day alarm enable 0 = disable, 1 = enable 0 houren [2] hour alarm enable 0 = disable, 1 = enable 0 minen [1] minute alarm enable 0 = disable, 1 = enable 0 secen [0] second alarm enable 0 = disable, 1 = enable 0
s3c2400 risc microprocessor real time clock 17- 6 alarm second data register (almsec) register address r/w description reset value almsec 0x15700054(l) 0x15700057(b) r/w (by byte) alarm second data register 0x00 almsec bit description initial state reserved [7] 0 secdata [6:4] bcd value for alarm second from 0 to 5 000 [3:0] from 0 to 9 0000 alarm min data register (almmin) register address r/w description reset value almmin 0x15700058(l) 0x1570005b(b) r/w (by byte) alarm minute data register 0x00 almmin bit description initial state reserved [7] 0 mindata [6:4] bcd value for alarm minute from 0 to 5 000 [3:0] from 0 to 9 0000 alarm hour data register (almhour) register address r/w description reset value almhour 0x1570005c(l) 0x1570005f(b) r/w (by byte) alarm hour data register 0x00 almhour bit description initial state reserved [7:6] 0 hourdata [5:4] bcd value for alarm hour from 0 to 2 00 [3:0] from 0 to 9 0000
s3c2400 risc microprocessor real time clock 17- 7 alarm day data register (almday) register address r/w description reset value almday 0x15700060(l) 0x15700063(b) r/w (by byte) alarm day data register 0x01 almday bit description initial state reserved [7:6] 0 daydata [5:4] bcd value for alarm day, from 0 to 28, 29, 30, 31 from 0 to 3 00 [3:0] from 0 to 9 0001 alarm mon data register (almmon) register address r/w description reset value almmon 0x15700064(l) 0x15700067(b) r/w (by byte) alarm month data register 0x01 almmon bit description initial state reserved [7:5] 0 mondata [4] bcd value for alarm month from 0 to 1 0 [3:0] from 0 to 9 0001 alarm year data register (almyear) register address r/w description reset value almyear 0x15700068(l) 0x1570006b(b) r/w (by byte) alarm year data register 0x00 almyear bit description initial state yeardata [7:0] bcd value for year from 00 to 99 0x00
s3c2400 risc microprocessor real time clock 17- 8 rtc round reset register (rtcrst) register address r/w description reset value rtcrst 0x1570006c(l) 0x1570006f(b) r/w (by byte) rtc round reset register 0x0. rtcrst bit description initial state srsten [3] round second reset enable 0 = disable, 1 = enable 0 seccr [2:0] round boundary for second carry generation. 011 = over than 30 sec 100 = over than 40 sec 101 = over than 50 sec note: if other values(0,1,2,6,7) are set, no second carry is generated. but second value can be reset. 00 bcd second register (bcdsec) register address r/w description reset value bcdsec 0x15700070(l) 0x15700073(b) r/w (by byte) bcd second register undef. bcdsec bit description initial state secdata [6:4] bcd value for second from 0 to 5 ? [3:0] from 0 to 9 ? bcd minute register (bcdmin) register address r/w description reset value bcdmin 0x15700074(l) 0x15700077(b) r/w (by byte) bcd minute register undef. bcdmin bit description initial state mindata [6:4] bcd value for minute from 0 to 5 ? [3:0] from 0 to 9 ?
s3c2400 risc microprocessor real time clock 17- 9 bcd hour register (bcdhour) register address r/w description reset value bcdhour 0x15700078(l) 0x1570007b(b) r/w (by byte) bcd hour register undef. bcdhour bit description initial state reserved [7:6] ? hourdata [5:4] bcd value for hour from 0 to 2 ? [3:0] from 0 to 9 ? bcd day register (bcdday) register address r/w description reset value bcdday 0x1570007c(l) 0x1570007f(b) r/w (by byte) bcd day register undef bcdday bit description initial state reserved [7:6] ? daydata [5:4] bcd value for day from 0 to 3 ? [3:0] from 0 to 9 ? bcd date register (bcddate) register address r/w description reset value bcddate 0x15700080(l) 0x15700083(b) r/w (by byte) bcd date register undef. bcddate bit description initial state reserved [7:3] ? datedata [2:0] bcd value for date from 1 to 7 ?
s3c2400 risc microprocessor real time clock 17- 10 bcd month register (bcdmon) register address r/w description reset value bcdmon 0x15700084(l) 0x15700087(b) r/w (by byte) bcd month register undef. bcdmon bit description initial state reserved [7:5] ? mondata [4] bcd value for month from 0 to 1 ? [3:0] from 0 to 9 ? bcd year register (bcdyear) register address r/w description reset value bcdyear 0x15700088(l) 0x1570008b(b) r/w (by byte) bcd year register undef. bcdyear bit description initial state yeardata [7:0] bcd value for year from 00 to 99 ?
s3c2400 risc microprocessor watchdog t imer 18- 1 18 watchdog timer overview the s3c2400 watchdog timer is used to resume the controller operation when it had been disturbed by malfunctions such as noise and system errors. it can be used as a normal 16-bit interval timer to request interrupt service. the watchdog timer generates the reset signal for 128 pclk cycles. features ? normal interval timer mode with interrupt request ? internal reset signal is activated for 128 pclk cycles when the timer count value reaches 0 (time-out).
watchdog timer s3c2 400 risc microprocessor 18- 2 watch-dog timer operation the functional block diagram of the watchdog timer is shown in figure 18-1. the watchdog timer uses pclk as its only source clock. to generate the corresponding watchdog timer clock, the pclk frequency is prescaled first, and the resulting frequency is divided again. reset signal generator wtcnt (down counter) pclk wtcon[4:3] wtdat reset 1/16 1/32 1/64 1/128 8-bit prescaler wtcon[15:8] wtcon[2] wtcon[0] interrupt mux figure 18-1. watch-dog timer block diagram the prescaler value and the frequency division factor are specified in the watchdog timer control register, wtcon. the valid prescaler values range from 0 to 2 8 -1. the frequency division factor can be selected as 16, 32, 64, or 128. use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle: t_watchdog = 1/( pclk / ( prescaler value + 1) / division_factor ) wtdat & wtcnt when the watchdog timer is enabled first, the value of wtdat (watchdog timer data register) cannot be automatically reloaded into the wtcnt (timer counter). for this reason, an initial value must be written to the watchdog timer count register, wtcnt, before the watchdog timer starts. consideration of debugging environment when s3c2400 is in debug mode using embedded ice, the watch-dog timer must not operate. the watch-dog timer can determine whether or not the current mode is the debug mode from the cpu core signal (dbgack signal). once the dbgack signal is asserted, the reset output of the watch-dog timer is not activated when the watchdog timer is expired.
s3c2400 risc microprocessor watchdog t imer 18- 3 watch-dog timer special registers watch-dog timer control register (wtcon) using the watch-dog timer control register, wtcon, you can enable/disable the watch-dog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watch-dog timer output. the watch-dog timer is used to resume the S3C2400X01 restart on mal-function after power-on; if controller restart is not desired, the watch-dog timer should be disabled. if the user wants to use the normal timer provided by the watch-dog timer, please enable the interrupt and disable the watch-dog timer. register address r/w description reset value wtcon 0x15300000 r/w watch-dog timer control register 0x8021 wtcon bit description initial state prescaler value [15:8] the prescaler value the valid range is from 0 to (2 8 -1) 0x80 reserved [7:6] reserved. these two bits must be 00 in normal operation. 00 watch-dog timer enable/disable [5] enable or disable bit of watch-dog timer. 0 = disable watch-dog timer 1 = enable watch-dog timer 1 clock select [4:3] this two bits determines the clock division factor. 00: 16 01: 32 10: 64 11: 128 00 interrupt enable/disable [2] enable or disable bit of the interrupt. 0 = disable interrupt generation 1 = enable interrupt generation 0 reserved [1] reserved. this bit must be 0 in normal operation 0 reset enable/disable [0] enable or disable bit of watch-dog timer output for reset signal: 1: asserts reset signal of the S3C2400X01 at watch-dog time-out 0: disables the reset function of the watch-dog timer. 1
watchdog timer s3c2 400 risc microprocessor 18- 4 watch-dog timer data register (wtdat) the watchdog timer data register, wtdat is used to specify the time-out duration. the content of wtdat can not be automatically loaded into the timer counter at initial watchdog timer operation. however, the first time-out occurs by using 0x8000(initial value), after then the value of wtdat will be automatically reloaded into wtcnt. register address r/w description reset value wtdat 0x15300004 r/w watch-dog timer data register 0x8000 wtdat bit description initial state count reload value [15:0] watch-dog timer count value for reload. 0x8000 watch-dog timer count register (wtcnt) the watchdog timer count register, wtcnt, contains the current count values for the watchdog timer during normal operation. note that the content of the watchdog timer data register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the watchdog timer count register must be set to an initial value before enabling it. register address r/w description reset value wtcnt 0x15300008 r/w watch-dog timer count register 0x8000 wtcnt bit description initial state count value [15:0] the current count value of the watch-dog timer 0x8000
s3c2400 risc microprocessor mmc interface 19- 1 19 mmc interface overview the s3c2400 multimediacard (mmc) interface can interface with mmc type (referenced mmca ver 2.11) serial data. there are four tokens in the mmc type serial data; transmit command, receive response, transmit data, receive data. mmc module needs to transfer these four tokens respectively. we will design mmc interface with four part division as block diagram. if mmc module transmits or receives data, each fifo should always operate. however, if mmc module transmits command or receives response, neither fifo nor dma mode are not supplied. features ? multimediacard protocol (ver 2.11) compatible ? 16 bytes fifo (depth 16) for the data transmission ? 16 bytes fifo (depth 16) for the data receiving. ? 40-bit command register ? 128-b it response register ? 8-bit prescaler logic (freq. = system clock / (2(p + 1))) ? crc7 & crc16 generator ? data fault error detection logic ? normal, interrupt, and dma transfer mode
s3c2400 risc microprocessor mmc interface 19- 2 block diagram 8bit prescaler mmcmd (5byte) mmrsp (16byte) txfifo (16byte) rxfifo (16byte) clock logic crc7 data transmitter data receiver crc16 data bus pclk mmclk tx_cmd rx_cmd tx_dat rx_dat 32 32 8 8 8 8 8 8 prescaler register response receiver command transmitter figure 19-1. mmc block diagram
s3c2400 risc microprocessor mmc interface 19- 3 mmc operation a serial clock line synchronizes shifting and sampling of the information on the two serial data lines. the transmission frequency is controlled by making the appropriate bit settings to the mmpre register. you can modify its frequency to adjust the baud rate data register value. programming procedure to program the mmc modules, follow these basic steps : 1. set baud rate prescaler register(mmpre). 2. set mmcon, and mmfcon to configure properly the mmc module and fifo, and block length register(mmlen). 3. wait 74 mmclk clock cycle in order to initialize the card. 4. write command 5byte to mmcmd 5. start command transmit and determine command types with setting mmcrr register. 6. tx data ? write data to data register(mmdat) while tx fifo is not beyond trigger level. 7. rx data ? data receiver starts operation when mmc module detects start bit in dat pin. user can read data from rx fifo when rx fifo reaches trigger level or rx fifo has the last data of a block. 8. confirm the end of mmc command operation when ncfin(normal command finish) flag, or dcfin(data command finish) flag of mmsta register is set 9. clear the corresponding flag(ncfin, or dcfin) of mmsta through writing one with this bit. steps for transmit by dma 1. dma is configured properly and the mmc is configured as dma start with mmc mode select bits. 2. if tx fifo is beyond trigger level, go to step 4. 3. the mmc requests dma service, and then dma transmits 1byte data to mmc module until fifo is full. 4. the mmc transmits the data to card. 5. go to step 2 until dma count is 0. steps for receive by dma 1. dma is configured properly and the mmc is configured as dma start with mmc mode select bits. 2. the mmc receives the data from card. 3. if rx fifo neither reaches trigger level nor has the last data of a block, go to step 2. 4. the mmc requests dma service, and then dma receives 1byte data from mmc module until fifo is empty. 5. go to step 2 until dma count is 0.
s3c2400 risc microprocessor mmc interface 19- 4 mmc special registers mmc control register (mmcon) register address r/w description reset value mmcon 0x15a00000( li/b, li/hw, li/w, bi/w) 0x15a00002( bi/hw) 0x15a00003( bi/b) r/w mmc control register 0x00 mmcon bit description initial state reserved [7:6] exception interrupt enable (einte) [5] determines mmc generate an interrupt if an exception(crc error etc) or transfer completion occur. 0 = disable, 1 = interrupt enable 0 mmc mode select (mmod) [4:3] determines how the mmc interface is read/written. 00 = polling mode, 01 = interrupt mode 10 = dma transmit mode, 11 = dma receive mode 00 prescaler enable (enpre) [2] determines what you want prescaler enable or not. 0 = counter reset, 1 = enable prescaler 0 clock polarity select (cpol) [1] determines an active high or active low clock. 0 = active high, 1 = active low 0 clock pending mode(pend) [0] determines clock pends when apb is not ready to transfer data. 0 = disable, 1 = clock pending mode enable 0 notes: 1. when clock pending mode state is disable, if receive data collision error occurs and invalid data transmit error occurs, mmsta[2], mmsta[3] is set. 2. ( li/b/hw/w): access by byte/half-word/word unit when the endian mode is little. ( bi/b/hw/w): access by byte/half-word/word unit when the endian mode is big.
s3c2400 risc microprocessor mmc interface 19- 5 mmc command related register (mmcrr) register address r/w description reset value mmcrr 0x15a00004( li/b, li/hw, li/w, bi/w) 0x15a00006( bi/hw) 0x15a00007( bi/b) r/w mmc command related register 0x00 mmcrr bit description initial state response type (rtyp) [7:6] determines what response type mmc command is. 00 = no response, 01 = short type (5 byte) 10 = short & busy type (5 byte), 11 = long type (16 byte) 00 multi block mode (multi) [5] determines whether mmc command type is multi or not. 0 = normal mode, 1 = multi mode 0 sequential mode (seq) [4] determines whether mmc command type is seq or not. 0 = normal mode, 1 = sequential mode 0 data stop command (stop) [3] determines whether mmc command function is stop or not. 0 = not stop command, 1 = stop command 0 data read command (rcmd) [2] determines whether mmc command function is read or not. 0 = not read command, 1 = read command 0 data write command (wcmd) [1] determines whether mmc command function is write or not. 0 = not write command, 1 = write command 0 command start (cmst) [0] determines whether mmc command operation starts or not. 0 = command ready, 1 = command start 0 note: when you are going to operate stop command, confirm transmit(or receive) all the data to send (or get). and then, you can execute stop command. but, in the case of sequential(seq) write( wcmd) command, you should but also watch tx fifo's count number whether zero or not.
s3c2400 risc microprocessor mmc interface 19- 6 mmcrr register setting according to multi media card cmd cmd no. operation rtyp multi seq stop rcmd wcmd finish flag cmd0 go idle 0 0 0 0 0 0 normal cmd2 all send cid 3 0 0 0 0 0 normal cmd4 set dsr 0 0 0 0 0 0 normal cmd7 card select 1 0 0 0 0 0 normal cmd7 card deselect 0 0 0 0 0 0 normal cmd9 send csd 3 0 0 0 0 0 normal cmd10 send cid 3 0 0 0 0 0 normal cmd11 read seq data 1 0 set 0 set 0 data cmd12 stop transfer 1 0 0 set 0 0 normal cmd15 go inactive state 0 0 0 0 0 0 normal cmd17 read single block 1 0 0 0 set 0 data cmd18 read multi block 1 set 0 0 set 0 data cmd20 write seq data 1 0 set 0 0 set data cmd24 write single block 1 0 0 0 0 set data cmd25 write multi block 1 set 0 0 0 set data cmd26 program cid 1 0 0 0 0 set data cmd27 program csd 1 0 0 0 0 set data cmd28 set write protect 2 0 0 0 0 0 normal cmd29 clr write protect 2 0 0 0 0 0 normal cmd30 send write protect 1 0 0 0 set 0 data cmd38 erase 2 0 0 0 0 0 normal other the other cmd 1 0 0 0 0 0 normal note: if you transmit cmd2 several times moer than the number of cards attatched, you must add to transmit dummy data through cmd bus. you can know the number of cards attatched when ncfin flag wll not set although 189 mmcclk cycles running(during the minimum length loop of 160 times) after starting cmd2. typical value of dummy data are 0x00, 0x00, 0x00, 0x00, 0x00(5bytes). you put these value in the mmcmd0, mmcmd1 register, and th en set mmcrr register to 0x01.
s3c2400 risc microprocessor mmc interface 19- 7 mmc fifo control register (mmfcon) register address r/w description reset value mmfcon 0x15a00008( li/b, li/hw, li/w, bi/w) 0x15a0000a( bi/hw) 0x15a0000b( bi/b) r/w mmc fifo control register 0x00 mmfcon bit description initial state reserved [7:6] tx fifo trigger level (tftrig) [5:4] determines trigger level of transmit fifo 00 = empty, 01 = 4 byte 10 = 8 byte 11 = 12 byte 00 rx fifo trigger level (rftrig) [3:2] determines trigger level of receive fifo. 00 = 4 byte, 01 = 8 byte 10 = 12 byte 11 = 16 byte 00 tx fifo reset (tfrst) [1] determines resetting for transmit fifo. 0 = normal mode, 1 = tx fifo reset 0 rx fifo reset (rfrst) [0] determines resetting for receive fifo. 0 = normal mode, 1 = rx fifo reset 0 note: you must always reset tx fifo or rx fifo, after completion multi command operation and seq command operation. fifo may have some of dummy data in these c ommands.
s3c2400 risc microprocessor mmc interface 19- 8 mmc status register (mmsta) register address r/w description reset value mmsta 0x15a0000c( li/b, li/hw, li/w, bi/w) 0x15a0000e( bi/hw) 0x15a0000f( bi/b) r/(c) mmc status register 0x00 mmsta bit description initial state reserved [7] response crc mismatch error (rcrc) [6] this flag is set when response token value is wrong. this flag is cleared by reading the mmsta with rcrc set. 0 = not occur, 1 = crc error occur 0 data read crc mismatch error (dcrc) [5] this flag is set when data reading token value is wrong. this flag is cleared by reading the mmsta with dcrc set. 0 = not occur, 1 = crc error occur 0 crc status error (crcs) [4] this flag is set when data writing token is wrong. this flag is cleared by reading the mmsta with crcs set. 0 = not occur, 1 = crc status error occur 0 invalid data transmit error (invl) [3] this flag is set when invalid data should be transmitted because there is no data in the transmit fifo. this flag is cleared by reading the mmsta with invl set. 0 = not detect, 1 = invalid data tx error detect 0 receive data collision error (rcol) [2] this flag is set when data collision occurs in the receive fifo. this flag is cleared by reading the mmsta with rcol set. 0 = not detect, 1 = collision error detect 0 data command finish (dcfin) [1] r/c this bit indicates that data transfer related command operation completes. this flag is cleared by setting to one this bit. 0 = not finish, 1 = data command finish normal command finish (ncfin) [0] r/c this bit indicates that normal command operation completes. this flag is cleared by setting to one this bit. 0 = not finish, 1 = normal command finish 0 notes: 1. dcfin bit is set after the data transfer 2. in case of the command with the response , ncfin bit is set after the response. in case of the command without the response, ncfin bit is set after the command transfer.
s3c2400 risc microprocessor mmc interface 19- 9 mmc fifo status register (mmfsta) register address r/w description reset value mmfsta 0x15a00010( li/hw, li/w, bi/w) 0x15a00012( bi/hw) r mmc fifo status register 0x0000 mmfsta bit description initial state reserved [15:12] tx fifo count (tfcnt) [11:8] number of data in transmit fifo 0000 rx fifo count (rfcnt) [7:4] number of data in receive fifo 0000 tx fifo full (tffull) [3] this bit automatically set to 1 whenever transmit fifo is full. 0 = 0 2 tx fifo 2 15, 1 = full 0 rx fifo full (rffull) [2] this bit automatically set to 1 whenever receive fifo is full. 0 = 0 2 rx fifo 2 15, 1 = full 0 tx fifo trigger level detect (tfdet) [1] this bit indicates that tx fifo reaches mmfcon's trigger level. 0 = not detect, 1 = detect 0 rx fifo trigger level detect (rfdet) [0] this bit indicates that rx fifo reaches mmfcon's trigger level or rx fifo has the last data of a block. 0 = not detect, 1 = detect 0 mmc baud rate prescaler register (mmpre) register address r/w description reset value mmpre 0x15a00014 ( li/b, li/hw, li/w, bi/w) 0x15a00016 ( bi/hw) 0x15a00017 ( bi/b) r/w mmc baud rate prescaler register 0x00 mmpre bit description initial state prescaler value [7:0] determines mmc clock rate as below equation. baud rate = pclk / 2 / ( prescaler value + 1) 0x00 mmc block length register (mmlen) register address r/w description reset value mmlen 0x15a00018( li/hw, li/w, bi/w) 0x15a0001a( bi/hw) r/w mmc block length register 0x0000 mmlen bit description initial state block length value [15:0] determines the block size to transfer data 0x0000
s3c2400 risc microprocessor mmc interface 19- 10
s3c2400 risc microprocessor mmc interface 19- 11 response crc7 register (mmcr7) register address r/w description reset value mmcr7 0x15a0001c( li/b, li/hw, li/w, bi/w) 0x15a0001e( bi/hw) 0x15a0001f( bi/b) r response crc7 register 0x00 rcrc7 bit description initial state response crc7 value [7:1] this field contains the response crc7 value. 0x00 response endbit [0] this field contains the response endbit. 0x0 mmc response status register 0 (mmrsp0) register address r/w description reset value mmrsp0 0x15a00020 r mmc response status register 0 0x00000000 mmrsp bit little big description initial state response register [31:24] 4 th byte 1 st byte this field contains the response value to be received over the mmc channel. 0x00 response register [23:16] 3 rd byte 2 nd byte this field contains the response value to be received over the mmc channel. 0x00 response register [15:8] 2 nd byte 3 rd byte this field contains the response value to be received over the mmc channel. 0x00 response register [7:0] 1 st byte 4 th byte this field contains the response value to be received over the mmc channel. 0x00 mmc response status register 1 (mmrsp1) register address r/w description reset value mmrsp1 0x15a00024 r mmc response status register 1 0x00000000 mmrsp bit little big description initial state response register [31:24] 8 th byte 5 th byte this field contains the response value to be received over the mmc channel. 0x00 response register [23:16] 7 th byte 6 th byte this field contains the response value to be received over the mmc channel. 0x00 response register [15:8] 6 th byte 7 th byte this field contains the response value to be received over the mmc channel. 0x00 response register [7:0] 5 th byte 8 th byte this field contains the response value to be received over the mmc channel. 0x00
s3c2400 risc microprocessor mmc interface 19- 12 mmc response status register 2 (mmrsp2) register address r/w description reset value mmrsp2 0x15a00028 r mmc response status register 2 0x00000000 mmrsp bit little big description initial state response register [31:24] 12 th byte 9 th byte this field contains the response value to be received over the mmc channel. 0x00 response register [23:16] 11 th byte 10 th byte this field contains the response value to be received over the mmc channel. 0x00 response register [15:8] 10 th byte 11 th byte this field contains the response value to be received over the mmc channel. 0x00 response register [7:0] 9 th byte 12 th byte this field contains the response value to be received over the mmc channel. 0x00 mmc response status register 3 (mmrsp3) register address r/w description reset value mmrsp3 0x15a0002c r mmc response status register 3 0x00000000 mmrsp bit little big description initial state response register [31:24] 16 th byte 13 th byte this field contains the response value to be received over the mmc channel. 0x00 response register [23:16] 15 th byte 14 th byte this field contains the response value to be received over the mmc channel. 0x00 response register [15:8] 14 th byte 15 th byte this field contains the response value to be received over the mmc channel. 0x00 response register [7:0] 13 th byte 16 th byte this field contains the response value to be received over the mmc channel. 0x00 mmc command register 0 (mmcmd0) register address r/w description reset value mmcmd0 0x15a00030( li/b, li/hw, li/w, bi/w) 0x15a00032( bi/hw) 0x15a00033( bi/b) r/w mmc command register 0 0x00 mmcmd bit description initial state command register (1 st byte) [7:0] this field contains the command value to be transmitted over the mmc channel. 0x00
s3c2400 risc microprocessor mmc interface 19- 13 mmc command register 1 (mmcmd1) register address r/w description reset value mmcmd1 0x15a00034 r/w mmc command register 1 0x00000000 mmcmd bit little big description initial state command register (2 nd byte) [31:24] 4 th byte 1 st byte this field contains the command value to be transmitted over the mmc channel. 0x00 command register (3 rd byte) [23:16] 3 rd byte 2 nd byte this field contains the command value to be transmitted over the mmc channel. 0x00 command register (4 th byte) [15:8] 2 nd byte 3 rd byte this field contains the command value to be transmitted over the mmc channel. 0x00 command register (5 th byte) [7:0] 1 st byte 4 th byte this field contains the command value to be transmitted over the mmc channel. 0x00 data receive crc16 buffer register (mmcr16) register address r/w description reset value mmcr16 0x15a00038( li/hw, li/w, bi/w) 0x15a0003a( bi/hw) r data read crc16 buffer register 0x0000 crc16b bit description initial state data read crc16 value [15:0] this field contains the data receive crc16 buffer value. 0x0000 mmc data register (mmdat) register address r/w description reset value mmdat 0x15a0003c( li/b, li/hw, li/w, bi/w) 0x15a0003e( bi/hw) 0x15a0003f( bi/b) r/w mmc data register 0x00 mmdat bit description initial state data register [7:0] this field contains the data to be transmitted or received over the mmc channel 0x00
s3c2400 risc microprocessor iic-bus interface 20- 1 20 iic-bus interface overview the s3c2400 risc microprocessor can support a multi-master iic-bus serial interface. a dedicated serial data line (sda) and a serial clock line (scl) carry information between bus masters and peripheral devices which are connected to the iic-bus. the sda and scl lines are bi-directional. in multi-master iic-bus mode, multiple s3c2400 risc microprocessors can receive or transmit serial data to or from slave devices. the master s3c2400, which can initiate a data transfer over the iic-bus, is responsible for terminating the transfer. standard bus arbitration procedure is used in this iic-bus in s3c2400. to control multi-master iic-bus operations, values must be written to the following registers: ? multi-master iic-bus control regi ster, iiccon ? multi-master iic-bus control/status register, iicstat ? multi-master iic-bus tx/rx data shift register, iicds ? multi-master iic-bus address register, iicadd when the iic-bus is free, the sda and scl lines should be both at high level. a high-to-low transition of sda can initiate a start condition. a low-to-high transition of sda can initiate a stop condition while scl remains steady at high level. the start and stop conditions can always be generated by the master devices. a 7-bit address value in the first data byte, which is put onto the bus after the start condition has been initiated, can determine the slave device which the bus master device has selected. the 8 th bit determines the direction of the transfer (read or write). every data byte put onto the sda line should total eight bits. the number of bytes which can be sent or received during the bus transfer operation is unlimited. data is always sent from most-significant bit (msb) first, and every byte should be immediately followed by an acknowledge (ack) bit.
s3c2400 risc microprocessor iic-bus interface 20- 2 pclk address register sda 4-bit prescaler iic-bus control logic iicstat iiccon comparator shift register shift register (iicds) data bus scl figure 20-1. iic-bus block diagram
s3c2400 risc microprocessor iic-bus interface 20- 3 the iic-bus interface the S3C2400X01 iic-bus interface has four operation modes: ? master transmitter mode ? master receive mode ? slave transmitter mode ? slave receive mode functional relationships among these operating modes are described below. start and stop conditions when the iic-bus interface is inactive, it is usually in slave mode. in other words, the interface should be in slave mode before detecting a start condition on the sda line.(a start condition can be initiated with a high-to-low transition of the sda line while the clock signal of scl is high) when the interface state is changed to the master mode, a data transfer on the sda line can be initiated and scl signal generated. a start condition can transfer a one-byte serial data over the sda line, and a stop condition can terminate the data transfer. a stop condition is a low-to-high transition of the sda line while scl is high. start and stop conditions are always generated by the master. the iic-bus is busy when a start condition is generated. a few clocks after a stop condition, the iic-bus will be free, again. when a master initiates a start condition, it should send a slave address to notify the slave device. the one byte of address field consist of a 7-bit address and a 1-bit transfer direction indicator (that is, write or read). if bit 8 is 0, it indicates a write operation(transmit operation); if bit 8 is 1, it indicates a request for data read(receive operation). the master will finish the transfer operation by transmitting a stop condition. if the master wants to continue the data transmission to the bus, it should generate another start condition as well as a slave address. in this way, the read- write operation can be performed in various formats. scl sda sda scl start condition stop condition figure 20-2. start and stop condition
s3c2400 risc microprocessor iic-bus interface 20- 4 data transfer format every byte placed on the sda line should be eight bits in length. the number of bytes which can be transmitted per transfer is unlimited. the first byte following a start condition should have the address field. the address field can be transmitted by the master when the iic-bus is operating in master mode. each byte should be followed by an acknowledgement (ack) bit. the msb bit of the serial data and addresses are always sent first. write mode format with 7-bit addresses "0" (write) data transferred (data + acknowledge) s slave address 7bits r/w a p data(1byte) a read mode format with 7-bit addresses "1" (read) data transferred (data + acknowledge) s slave address 7 bits r/w a p data a write mode format with 10-bit addresses "0" (write) data transferred (data + acknowledge) p data a s slave address 1st 7 bits r/w a slave address 2nd byte a 11110xx notes: 1. s: start, rs: repeat start, p: stop, a: acknowledge 2. : from master to slave, : from slave to master figure 20-3. iic-bus interface data format
s3c2400 risc microprocessor iic-bus interface 20- 5 acknowledgement signal from receiver s 1 2 7 8 9 1 2 9 acknowledgement signal from receiver msb ack byte complete, interrupt within receiver clock line held low until the interrupt pending flahg (iiccon[4]) is cleared. figure 20-4. data transfer on the iic-bus ack signal transmission to finish a one-byte transfer operation completely, the receiver should send an ack bit to the transmitter. the ack pulse should occur at the ninth clock of the scl line. eight clocks are required for the one-byte data transfer. the master should generate the clock pulse required to transmit the ack bit. the transmitter should release the sda line by making the sda line high when the ack clock pulse is received. the receiver should also drive the sda line low during the ack clock pulse so that the sda is low during the high period of the ninth scl pulse. the ack bit transmit function can be enabled or disabled by software (iicstat). however, the ack pulse on the ninth clock of scl is required to complete a one-byte data transfer operation. data output by transmitter data output by receiver scl from master start condition clock pulse for acknowledgment clock to output 9 8 7 s 1 2 figure 20-5. acknowledge on the iic-bus
s3c2400 risc microprocessor iic-bus interface 20- 6 read-write operation in the transmitter mode, after the data is transferred, the iic-bus interface will wait until iicds(iic-bus data shift register) is written by a new data. until the new data is written, the scl line will be held low. after the new data is written to iicds register, the scl line will be released. the S3C2400X01 should hold the interrupt to identify the completion of current data transfer. after the cpu receives the interrupt request, it should write a new data into iicds, again. in the receive mode, after a data is received, the iic-bus interface will wait until iicds register is read. until the new data is read out, the scl line will be held low. after the new data is read out from iicds register, the scl line will be released. the S3C2400X01 should hold the interrupt to identify the completion of the new data reception. after the cpu receives the interrupt request, it should read the data from iicds. bus arbitration procedures arbitration takes place on the sda line to prevent the contention on the bus between two masters. if a master with a sda high level detects another master with a sda active low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. the arbitration procedure will be extended until the sda line turns high. however when the masters simultaneously lower the sda line, each master should evaluate whether or not the mastership is allocated to itself. for the purpose of evaluation, each master should detect the address bits. while each master generates the slaver address, it should also detect the address bit on the sda line because the lowering of sda line is stronger than maintaining high on the line. for example, one master generates a low as first address bit, while the other master is maintaining high. in this case, both masters will detect low on the bus because low is stronger than high even if first master is trying to maintain high on the line. when this happens, low(as the first bit of address) -generating master will get the mastership and high(as the first bit of address) - generating master should withdraw the mastership. if both masters generate low as the first bit of address, there should be an arbitration for second address bit, again. this arbitration will continue to the end of last address bit. abort conditions if a slave receiver can not acknowledge the confirmation of the slave address, it should hold the level of the sda line high. in this case, the master should generate a stop condition and to abort the transfer. if a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ack after the last data byte received from the slave. the slave transmitter should then release the sda to allow a master to generate a stop condition. configuring the iic-bus to control the frequency of the serial clock (scl), the 4-bit prescaler value can be programmed in the iiccon register. the iic-bus interface address is stored in the iic-bus address register, iicadd. (by default, the iic-bus interface address is an unknown value.)
s3c2400 risc microprocessor iic-bus interface 20- 7 flowcharts of the operations in each mode the following steps must be executed before any iic tx/rx operations. 1) write own slave address on iicadd register if needed. 2) set iiccon register. a) enable interrupt b) define scl period 3) set iicstat to enable serial output. write slave address to iicds write 0xf0(m/t start) to iicstat the data of the iicds is transmitted ack period and then interrupt is pending write 0xd0(m/t stop) to iicstat write new data trasnmitted to iicds stop? clear pending bit to resume the data of the iicds is shifted to sda start master tx mode has been configured. clear pending bit wait until the stop condition takes effect. end y n figure 20-6. operations for master/transmitter mode
s3c2400 risc microprocessor iic-bus interface 20- 8 write slave address to iicds write 0xb0(m/r start) to iicstat the data of the iicds(slave address) is transmitted ack period and then interrupt is pending write 0x90(m/r stop) to iicstat read a new data from iicds stop? clear pending bit to resume sda is shifted to iicds start master rx mode has been configured. clear pending bit wait until the stop condition takes effect. end y n figure 20-7. operations for master/receiver mode
s3c2400 risc microprocessor iic-bus interface 20- 9 iic detects start signal. and, iicds receives data. iic compares iicadd and iicds(the received slave address) write data to iicds the iic address match interrupt is generated clear pending bit to resume. the data of the iicds is shifted to sda start slave tx mode has been configured. end matched? n y stop? interrupt is pending n y figure 20-8. operations for slave/transmitter mode
s3c2400 risc microprocessor iic-bus interface 20- 10 iic detects start signal. and, iicds receives data. iic compares iicadd and iicds(the received slave address) read iicds the iic address match interrupt is generated clear pending bit to resume. sda is shifted to iicds start slave rx mode has been configured. end matched? n y stop? interrupt is pending n y figure 20-9. operations for slave / receiver mode
s3c2400 risc microprocessor iic-bus interface 20- 11 iic-bus interface special registers multi-master iic-bus control register (iiccon) register address r/w description reset value iiccon 0x15400000 r/w iic-bus control register 0000_xxxx iiccon bit description initial state acknowledge enable (1) [7] iic-bus acknowledge enable bit. 0=disable ack generation 1=enable ack generation in tx mode, the iicsda is free in the ack time. in rx mode, the iicsda is l in the ack time. 0 tx clock source selection [6] source clock of iic-bus transmit clock prescaler selection bit. 0= iicclk = f pclk /16 1= iicclk = f pclk /512 0 tx/rx interrupt enable (5) [5] iic-bus tx/rx interrupt enable/disable bit. 0=disable interrupt, 1=enable interrupt 0 interrupt pending flag (2) (3) [4] iic-bus tx/rx interrupt pending flag. writing 1 is impossible. when this bit is read as 1, the iicscl is tied to l and the iic is stopped. to resume the operation, clear this bit as 0. 0 = 1) read) no interrupt pending 2) write) clear pending condition & resume the operation. 1 = 1) read) interrupt is pending 2) write) n/a 0 transmit clock value (4) [3:0] iic-bus transmit clock prescaler iic-bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formula: tx clock = iicclk/(iiccon[3:0]+1) undefined notes: 1. interfacing with eeprom, the ack generation may be disabled before reading the last data in order to generate the stop condition in rx mode. 2. a iic-bus interrupt occurs 1)when a 1-byte transmit or receive operation is completed, 2)when a general c all or a slave address match occurs, or 3) if bus arbitration fails. 3. to time the setup time of iicsda before iisscl rising edge, iicds has to be written before clearing the iic interrupt pending bit. 4. iicclk is determined by iiccon[6]. tx clock can vary by scl transition time. when iiccon[6]=0, iiccon[3:0]=0x0 or 0x1 is not available. 5. if the iicon[5]=0, iicon[4] does not operate correctly. so, it is recommended to set iiccon[4]=1, although you does not use the iic interrup t.
s3c2400 risc microprocessor iic-bus interface 20- 12 multi-master iic-bus control/status register (iicstat) register address r/w description reset value iicstat 0x15400004 r/w iic-bus control/status register 0000_0000 iicstat bit description initial state mode selection [7:6] iic-bus master/slave tx/rx mode select bits: 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode 0 busy signal status / start stop condition [5] iic-bus busy signal status bit: 0 = read) iic-bus not busy. (iic always senses bus start/stop condition.) write) iic-bus stop signal generation 1 = read) iic-bus busy write) iic-bus start signal generation. the data in iicds will be transferred automatically just after the start signal. also, the delay to check the start condition is inserted automatically. 0 serial output enable [4] iic-bus data output enable/disable bit: 0=disable rx/ tx, 1=enable rx/ tx 0 arbitration status flag [3] iic-bus arbitration procedure status flag bit: 0 = bus arbitration successful 1 = bus arbitration failed during serial i/o 0 address-as-slave status flag [2] iic-bus address-as-slave status flag bit: 0 = cleared when start/stop condition was detected. 1 = received slave address matches the address value in the iicadd. 0 address zero status flag [1] iic-bus address zero status flag bit: 0 = cleared when start/stop condition was detected at the sda/scl line. 1 = received slave address is 00000000b 0 last-received bit status flag [0] iic-bus last-received bit status flag bit 0 = last-received bit is 0 (ack was received). 1 = last-receive bit is 1 (ack was not received). 0
s3c2400 risc microprocessor iic-bus interface 20- 13 multi-master iic-bus address register (iicadd) register address r/w description reset value iicadd 0x15400008 r/w iic-bus address register xxxx_xxxx iicadd bit description initial state slave address [7:0] 7-bit slave address, latched from the iic-bus: when serial output enable=0 in the iicstat, iicadd is write- enabled. the iicadd value can be read any time, regardless of the current serial output enable bit (iicstat) setting. iicadd is used only when the iic mode is selected to slave receive/transmit mode. slave address = [7:1] not mapped = [0] xxxx_xxxx multi-master iic-bus transmit/receive data shift register (iicds) register address r/w description reset value iicds 0x1540000c r/w iic-bus transmit/receive data shift register xxxx_xxxx iicds bit description initial state data shift [7:0] 8-bit data shift register for iic-bus tx/rx operation: when serial output enable = 1 in the iicstat, iicds is write- enabled. the iicds value can be read any time, regardless of the current serial output enable bit (iicstat) setting note: the bit[0] of the data, which is transferred just after start condition, is determined by the mode selection bit. if the mode selection bit is "receive", the bit will be 1(read). if the mode selection bit is "transmit", the bit will be 0(write). xxxx_xxxx
s3c2400 risc microprocessor iic-bus interface 20- 14 notes
s3c2400 risc microprocessor iis-bus interface 21- 1 21 iis-bus interface overview many digital audio systems are introduced into the consumer audio market, including compact disc, digital audio tapes, digital sound processors, and digital tv sound. the s3c2400 iis (inter-ic sound) bus interface can be used to implement a codec interface to an external 8/16-bit stereo audio codec ic for mini-disc and portable applications. it supports the iis bus data format and msb-justified data format. iis bus interface provides dma transfer mode for fifo access instead of an interrupt. it can transmit or receive data simultaneously as well as transmit or receive only. features ? iis, msb-justified format compatible ? 8/16-bit data per channel ? 16, 32, 48fs (sampling frequency) serial bit clock per channel ? 256, 384fs master clock ? programmable frequency divider for master clock and codec clock ? 32 bytes (2 16) fifo for transmit and receive ? normal and dma transfer mode
iis-bus interface s3c2400 risc microprocessor 21- 2 block diagram addr data cntl pclk brfc ipsr_a ipsr_b txfifo rxfifo sclkg chnc sftr lrck sclk sd cdclk figure 21-1. iis-bus block diagram functional descriptions bus interface, register bank, and state machine (brfc) - bus interface logic and fifo access are controlled by the state machine. 5-bit dual prescaler (ipsr) - one prescaler is used as the master clock generator of the iis bus interface and the other is used as the external codec clock generator. 16-byte fifos (txfifo, rxfifo) - in transmit data transfer, data are written to txfifo, and, in the receive data transfer, data are read from rxfifo. master iisclk generaor (sclkg) - in master mode, serial bit clock is generated from the master clock. channel generator and state machine (chnc) - iisclk and iislrck are generated and controlled by the channel state machine. 16-bit shift register (sftr) - parallel data is shifted to serial data output in the transmit mode, and serial data input is shifted to parallel data in the receive mode.
s3c2400 risc microprocessor iis-bus interface 21- 3 transmit or receive only mode normal transfer iis control register has fifo ready flag bits for transmit and receive fifo. when fifo is ready to transmit data, the fifo ready flag is set to '1' if transmit fifo is not empty. if transmit fifo is empty, fifo ready flag is set to '0'. when receive fifo is not full, the fifo ready flag for receive fifo is set to '1' ; it indicates that fifo is ready to receive data. if receive fifo is full, fifo ready flag is set to '0'. these flags can determine the time that cpu is to write or read fifos. serial data can be transmitted or received while cpu is accessing transmit and receive fifos in this way. dma transfer in this mode, transmit or receive fifo access is made by the dma controller. dma service request in transmit or receive mode is made by the fifo ready flag automatically. transmit and receive mode in this mode, iis bus interface can transmit and receive data simultaneously.
iis-bus interface s3c2400 risc microprocessor 21- 4 audio serial interface format iis-bus format the iis bus has four lines, serial data input (iisdi), serial data output (iisdo), left/right channel select (iislrck), and serial bit clock (iisclk); the device generating iislrck and iisclk is the master. serial data is transmitted in 2's complement with the msb first. the msb is transmitted first because the transmitter and receiver may have different word lengths. it is not necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. when the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to '0') for data transmission. if the receiver is sent more bits than its word length, the bits after the lsb are ignored. on the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. and so, the msb has a fixed position, whereas the position of the lsb depends on the word length. the transmitter always sends the msb of the next word at one clock period after the iislrck change. serial data sent by the transmitter may be synchronized with either the trailing (high to low) or the leading (low to high) edge of the clock signal. however, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. the lr channel select line indicates the channel being transmitted. iislrck may change either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. in the slave, this signal is latched on the leading edge of the clock signal. the iislrck line changes one clock period before the msb is transmitted. this allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. furthermore, it enables the receiver to store the previous word and clear the input for the next word. msb(left) justified msb / left justified bus has the same lines as the iis format. it is only different with the iis bus that transmitter always sends the msb of the next word when the iislrck change.
s3c2400 risc microprocessor iis-bus interface 21- 5 iis-bus format (n=8 or 16) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) lrck sclk sd left right left msb-justified format (n=8 or 16) 2nd bit n-1th bit lsb (last) msb (1st) 2nd bit n-1th bit lsb (last) lrck sclk sd left right msb (1st) figure 21-2. iis-bus and msb(left)-justified data interface formats sampling frequency and master clock master clock frequency (pclk) can be selected by sampling frequency as shown in table 21-1. because pclk is made by iis prescaler, the prescaler value and pclk type(256 or 384fs) should be determined properly. serial bit clock frequency type (16/32/48fs) can be selected by the serial bit per channel and pclk as shown in table 21-2. table 21-1 codec clock (codeclk = 256 or 384fs) iislrck ( fs) 8.000 khz 11.025 khz 16.000 khz 22.050 khz 32.000 khz 44.100 khz 48.000 khz 64.000 khz 88.200 khz 96.000 khz 256fs codeclk 2.0480 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 (mhz) 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 table 21-2 usable serial bit clock frequency (iisclk = 16 or 32 or 48fs) serial bit per channel 8-bit 16-bit serial clock frequency (iisclk) @codeclk=256fs 16fs, 32fs 32fs @codeclk=384fs 16fs, 32fs, 48fs 32fs, 48fs
iis-bus interface s3c2400 risc microprocessor 21- 6 iis-bus interface special registers iis control register (iiscon) register address r/w description reset value iiscon 0x15508000( li/hw, li/w, bi/w) 0x15508002( bi/hw) r/w iis control register 0x100 iiscon bit description initial state left/right channel index (read only) [8] 0 = left channel 1 = right channel 1 transmit fifo ready flag (read only) [7] 0 = fifo is not ready (empty) 1 = fifo is ready (not empty) 0 receive fifo ready flag (read only) [6] 0 = fifo is not ready (full) 1 = fifo is ready (not full) 0 transmit dma service request enable [5] 0 = request disable 1 = request enable 0 receive dma service request enable [4] 0 = request disable 1 = request enable 0 transmit channel idle command [3] in idle state the iislrck is inactive(pause tx) 0 = channel not idle 1 = channel idle 0 receive channel idle command [2] in idle state the iislrck is inactive(pause rx) 0 = channel not idle 1 = channel idle 0 iis prescaler enable [1] 0 = prescaler disable 1 = prescaler enable 0 iis interface enable (start) [0] 0 = iis disable (stop) 1 = iis enable (start) 0 notes: 1. the iiscon register can be accessed by byte, halfword and word unit using strb/strh/str and ldrb/ldrh/ldr instructions or char/short int/ int type pointer in little/big endian mode. 2. ( li/b/hw/w): access by byte/ halfword/word unit when the endian mode is little. ( bi/b/hw/w): access by byte/ halfword/word unit when the endian mode is big.
s3c2400 risc microprocessor iis-bus interface 21- 7 iis mode register (iismod) register address r/w description reset value iismod 0x15508004( li/w, li/hw, bi/w) 0x15508006( bi/hw) r/w iis mode register 0x0 iismod bit description initial state master/slave mode select [8] 0 = master mode (iislrck and iisclk are output mode) 1 = slave mode (iislrck and iisclk are input mode) 0 transmit/receive mode select [7:6] 00 = no transfer 01 = receive mode 10 = transmit mode 11 = transmit and receive mode 00 active level of left/right channel [5] 0 = low for left channel (high for right channel) 1 = high for left channel (low for right channel) 0 serial interface format [4] 0 = iis compatible format 1 = msb (left)-justified format 0 serial data bit per channel [3] 0 = 8-bit 1 = 16-bit 0 master clock frequency select [2] 0 = 256fs 1 = 384fs ( fs: sampling frequency) 0 serial bit clock frequency select [1:0] 00 = 16fs 01 = 32fs 10 = 48fs 11 = n/a 00 notes: 1. the iismod register can be accessed by halfword and word unit using strh/str and ldrh/ldr instructions or short int/ int type pointer in little/big endian mode. 2. ( li/hw/w): access by halfword/word unit when the endian mode is little. ( bi/hw/w): access by halfword/word unit when the endian mode is big.
iis-bus interface s3c2400 risc microprocessor 21- 8 iis prescaler register (iispsr) register address r/w description reset value iispsr 0x15508008( li/hw, li/w, bi/w) 0x1550800a( bi/hw) r/w iis prescaler register 0x0 iispsr bit description initial state prescaler control a [9:5] data value: 0 ? 31 note: prescaler a makes the master clock that is used the internal block and division factor is n+1. 0 prescaler control b [4:0] data value: 0 ? 31 note: prescaler b makes the master clock that is used the external block and division factor is n+1. 000 notes: 1. the iispsr register can be accessed by byte, halfword and word unit using strb/strh/str and ldrb/ldrh/ldr instructions or char/short int/ int type pointer in little/big endian mode. 2. ( li/b/hw/w): access by byte/ halfword/word unit when the endian mode is little. ( bi/b/hw/w): access by byte/ halfword/word unit when the endian mode is big. iis fifo control register (iisfcon) register address r/w description reset value iisfcon 0x1550800c( li/hw, li/w, bi/w) 0x1550800e( bi/hw) r/w iis fifo interface register 0x0 iisfcon bit description initial state transmit fifo access mode select [11] 0 = normal access mode 1 = dma access mode 0 receive fifo access mode select [10] 0 = normal access mode 1 = dma access mode 0 transmit ffo enable [9] 0 = fifo disable 1 = fifo enable 0 receive fifo enable [8] 0 = fifo disable 1 = fifo enable 0 transmit fifo data count (read only) [7:4] data count value = 0 ~ 8 000 receive fifo data count (read only) [3:0] data count value = 0 ~ 8 000 notes: 1. the iisfcon register can be accessed by halfword and word unit using strh/str and ldrh/ldr instructions or short int/ int type pointer in little/big endian mode. 2. ( li/hw/w): access by halfword/word unit when the endian mode is little. ( bi/hw/w): access by halfword/word unit when the endian mode is big.
s3c2400 risc microprocessor iis-bus interface 21- 9 iis fifo register (iisfif) iis bus interface contains two 16-byte fifo for the transmit and receive mode. each fifo has 16-width and 8-depth form, which allows the fifo to handles data by halfword unit regardless of valid data size. transmit and receive fifo access is performed through fifo entry; the address of fentry is 0x15508010. register address r/w description reset value iisfif 0x15508010( li/hw) 0x15508012( bi/hw) r/w iis fifo register 0x0 iisfif bit description initial state fentry [15:0] transmit/receive data for iis 0 notes: 1. the iisfif register can be accessed by halfword and word unit using strh and ldrh instructions or short int type pointer in little/big endian mode. 2. ( li/hw): access by halfword unit when the endian mode is little. ( bi/hw): access by halfword unit when the endian mode is big.
iis-bus interface s3c2400 risc microprocessor 21- 10 notes
s3c2400 risc microprocessor iis-bus interface 21- 1 21 iis-bus interface overview many digital audio systems are introduced into the consumer audio market, including compact disc, digital audio tapes, digital sound processors, and digital tv sound. the s3c2400 iis (inter-ic sound) bus interface can be used to implement a codec interface to an external 8/16-bit stereo audio codec ic for mini-disc and portable applications. it supports the iis bus data format and msb-justified data format. iis bus interface provides dma transfer mode for fifo access instead of an interrupt. it can transmit or receive data simultaneously as well as transmit or receive only. features ? iis, msb-justified format compatible ? 8/16-bit data per channel ? 16, 32, 48fs (sampling frequency) serial bit clock per channel ? 256, 384fs master clock ? programmable frequency divider for master clock and codec clock ? 32 bytes (2 16) fifo for transmit and receive ? normal and dma transfer mode
iis-bus interface s3c2400 risc microprocessor 21- 2 block diagram addr data cntl pclk brfc ipsr_a ipsr_b txfifo rxfifo sclkg chnc sftr lrck sclk sd cdclk figure 21-1. iis-bus block diagram functional descriptions bus interface, register bank, and state machine (brfc) - bus interface logic and fifo access are controlled by the state machine. 5-bit dual prescaler (ipsr) - one prescaler is used as the master clock generator of the iis bus interface and the other is used as the external codec clock generator. 16-byte fifos (txfifo, rxfifo) - in transmit data transfer, data are written to txfifo, and, in the receive data transfer, data are read from rxfifo. master iisclk generaor (sclkg) - in master mode, serial bit clock is generated from the master clock. channel generator and state machine (chnc) - iisclk and iislrck are generated and controlled by the channel state machine. 16-bit shift register (sftr) - parallel data is shifted to serial data output in the transmit mode, and serial data input is shifted to parallel data in the receive mode.
s3c2400 risc microprocessor iis-bus interface 21- 3 transmit or receive only mode normal transfer iis control register has fifo ready flag bits for transmit and receive fifo. when fifo is ready to transmit data, the fifo ready flag is set to '1' if transmit fifo is not empty. if transmit fifo is empty, fifo ready flag is set to '0'. when receive fifo is not full, the fifo ready flag for receive fifo is set to '1' ; it indicates that fifo is ready to receive data. if receive fifo is full, fifo ready flag is set to '0'. these flags can determine the time that cpu is to write or read fifos. serial data can be transmitted or received while cpu is accessing transmit and receive fifos in this way. dma transfer in this mode, transmit or receive fifo access is made by the dma controller. dma service request in transmit or receive mode is made by the fifo ready flag automatically. transmit and receive mode in this mode, iis bus interface can transmit and receive data simultaneously.
iis-bus interface s3c2400 risc microprocessor 21- 4 audio serial interface format iis-bus format the iis bus has four lines, serial data input (iisdi), serial data output (iisdo), left/right channel select (iislrck), and serial bit clock (iisclk); the device generating iislrck and iisclk is the master. serial data is transmitted in 2's complement with the msb first. the msb is transmitted first because the transmitter and receiver may have different word lengths. it is not necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. when the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to '0') for data transmission. if the receiver is sent more bits than its word length, the bits after the lsb are ignored. on the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. and so, the msb has a fixed position, whereas the position of the lsb depends on the word length. the transmitter always sends the msb of the next word at one clock period after the iislrck change. serial data sent by the transmitter may be synchronized with either the trailing (high to low) or the leading (low to high) edge of the clock signal. however, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge. the lr channel select line indicates the channel being transmitted. iislrck may change either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. in the slave, this signal is latched on the leading edge of the clock signal. the iislrck line changes one clock period before the msb is transmitted. this allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. furthermore, it enables the receiver to store the previous word and clear the input for the next word. msb(left) justified msb / left justified bus has the same lines as the iis format. it is only different with the iis bus that transmitter always sends the msb of the next word when the iislrck change.
s3c2400 risc microprocessor iis-bus interface 21- 5 iis-bus format (n=8 or 16) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) lrck sclk sd left right left msb-justified format (n=8 or 16) 2nd bit n-1th bit lsb (last) msb (1st) 2nd bit n-1th bit lsb (last) lrck sclk sd left right msb (1st) figure 21-2. iis-bus and msb(left)-justified data interface formats sampling frequency and master clock master clock frequency (pclk) can be selected by sampling frequency as shown in table 21-1. because pclk is made by iis prescaler, the prescaler value and pclk type(256 or 384fs) should be determined properly. serial bit clock frequency type (16/32/48fs) can be selected by the serial bit per channel and pclk as shown in table 21-2. table 21-1 codec clock (codeclk = 256 or 384fs) iislrck ( fs) 8.000 khz 11.025 khz 16.000 khz 22.050 khz 32.000 khz 44.100 khz 48.000 khz 64.000 khz 88.200 khz 96.000 khz 256fs codeclk 2.0480 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 (mhz) 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 table 21-2 usable serial bit clock frequency (iisclk = 16 or 32 or 48fs) serial bit per channel 8-bit 16-bit serial clock frequency (iisclk) @codeclk=256fs 16fs, 32fs 32fs @codeclk=384fs 16fs, 32fs, 48fs 32fs, 48fs
iis-bus interface s3c2400 risc microprocessor 21- 6 iis-bus interface special registers iis control register (iiscon) register address r/w description reset value iiscon 0x15508000( li/hw, li/w, bi/w) 0x15508002( bi/hw) r/w iis control register 0x100 iiscon bit description initial state left/right channel index (read only) [8] 0 = left channel 1 = right channel 1 transmit fifo ready flag (read only) [7] 0 = fifo is not ready (empty) 1 = fifo is ready (not empty) 0 receive fifo ready flag (read only) [6] 0 = fifo is not ready (full) 1 = fifo is ready (not full) 0 transmit dma service request enable [5] 0 = request disable 1 = request enable 0 receive dma service request enable [4] 0 = request disable 1 = request enable 0 transmit channel idle command [3] in idle state the iislrck is inactive(pause tx) 0 = channel not idle 1 = channel idle 0 receive channel idle command [2] in idle state the iislrck is inactive(pause rx) 0 = channel not idle 1 = channel idle 0 iis prescaler enable [1] 0 = prescaler disable 1 = prescaler enable 0 iis interface enable (start) [0] 0 = iis disable (stop) 1 = iis enable (start) 0 notes: 1. the iiscon register can be accessed by byte, halfword and word unit using strb/strh/str and ldrb/ldrh/ldr instructions or char/short int/ int type pointer in little/big endian mode. 2. ( li/b/hw/w): access by byte/ halfword/word unit when the endian mode is little. ( bi/b/hw/w): access by byte/ halfword/word unit when the endian mode is big.
s3c2400 risc microprocessor iis-bus interface 21- 7 iis mode register (iismod) register address r/w description reset value iismod 0x15508004( li/w, li/hw, bi/w) 0x15508006( bi/hw) r/w iis mode register 0x0 iismod bit description initial state master/slave mode select [8] 0 = master mode (iislrck and iisclk are output mode) 1 = slave mode (iislrck and iisclk are input mode) 0 transmit/receive mode select [7:6] 00 = no transfer 01 = receive mode 10 = transmit mode 11 = transmit and receive mode 00 active level of left/right channel [5] 0 = low for left channel (high for right channel) 1 = high for left channel (low for right channel) 0 serial interface format [4] 0 = iis compatible format 1 = msb (left)-justified format 0 serial data bit per channel [3] 0 = 8-bit 1 = 16-bit 0 master clock frequency select [2] 0 = 256fs 1 = 384fs ( fs: sampling frequency) 0 serial bit clock frequency select [1:0] 00 = 16fs 01 = 32fs 10 = 48fs 11 = n/a 00 notes: 1. the iismod register can be accessed by halfword and word unit using strh/str and ldrh/ldr instructions or short int/ int type pointer in little/big endian mode. 2. ( li/hw/w): access by halfword/word unit when the endian mode is little. ( bi/hw/w): access by halfword/word unit when the endian mode is big.
iis-bus interface s3c2400 risc microprocessor 21- 8 iis prescaler register (iispsr) register address r/w description reset value iispsr 0x15508008( li/hw, li/w, bi/w) 0x1550800a( bi/hw) r/w iis prescaler register 0x0 iispsr bit description initial state prescaler control a [9:5] data value: 0 ? 31 note: prescaler a makes the master clock that is used the internal block and division factor is n+1. 0 prescaler control b [4:0] data value: 0 ? 31 note: prescaler b makes the master clock that is used the external block and division factor is n+1. 000 notes: 1. the iispsr register can be accessed by byte, halfword and word unit using strb/strh/str and ldrb/ldrh/ldr instructions or char/short int/ int type pointer in little/big endian mode. 2. ( li/b/hw/w): access by byte/ halfword/word unit when the endian mode is little. ( bi/b/hw/w): access by byte/ halfword/word unit when the endian mode is big. iis fifo control register (iisfcon) register address r/w description reset value iisfcon 0x1550800c( li/hw, li/w, bi/w) 0x1550800e( bi/hw) r/w iis fifo interface register 0x0 iisfcon bit description initial state transmit fifo access mode select [11] 0 = normal access mode 1 = dma access mode 0 receive fifo access mode select [10] 0 = normal access mode 1 = dma access mode 0 transmit ffo enable [9] 0 = fifo disable 1 = fifo enable 0 receive fifo enable [8] 0 = fifo disable 1 = fifo enable 0 transmit fifo data count (read only) [7:4] data count value = 0 ~ 8 000 receive fifo data count (read only) [3:0] data count value = 0 ~ 8 000 notes: 1. the iisfcon register can be accessed by halfword and word unit using strh/str and ldrh/ldr instructions or short int/ int type pointer in little/big endian mode. 2. ( li/hw/w): access by halfword/word unit when the endian mode is little. ( bi/hw/w): access by halfword/word unit when the endian mode is big.
s3c2400 risc microprocessor iis-bus interface 21- 9 iis fifo register (iisfif) iis bus interface contains two 16-byte fifo for the transmit and receive mode. each fifo has 16-width and 8-depth form, which allows the fifo to handles data by halfword unit regardless of valid data size. transmit and receive fifo access is performed through fifo entry; the address of fentry is 0x15508010. register address r/w description reset value iisfif 0x15508010( li/hw) 0x15508012( bi/hw) r/w iis fifo register 0x0 iisfif bit description initial state fentry [15:0] transmit/receive data for iis 0 notes: 1. the iisfif register can be accessed by halfword and word unit using strh and ldrh instructions or short int type pointer in little/big endian mode. 2. ( li/hw): access by halfword unit when the endian mode is little. ( bi/hw): access by halfword unit when the endian mode is big.
iis-bus interface s3c2400 risc microprocessor 21- 10 notes
s3c2400 risc microprocessor spi interface 22 - 1 22 spi interface overview the s3c2400 serial peripheral interface(spi) can interface the serial data transfer. there are two 8bit shift register for transmission and receiving, respectively. during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially) 8bit serial data at a frequency determined by its corresponding control register settings. if you want only to transmit, you may treat the received data as dummy. otherwise, if you want only to receive, you should transmit dummy '1' data. there are 4 i/o pin signals associated with spi transfers: the sck, the miso data line, the mosi data line, and the active low /ss pin. features ? spi protocol (ver 2.11) compatible ? 8-bit shift register for transm it ? 8-bit shift register for receive ? 8-bit prescaler logic ? polling, interrupt, and dma transfer mode
s3c2400 risc microprocessor spi interface 22 - 2 block diagram tx 8bit shift reg rx 8bit shift reg lsb msb lsb msb pin control logic miso clock logic prescaler register 8bit prescaler status register apb i/f (int dma) mosi sck /ss data bus pclk spi miso spi mosi spi clk nss mulf dcol redy int req ack mstr clock spi clock (master) cpol cpha s m m s s m out in 8 8 figure 22-1. spi block diagram
s3c2400 risc microprocessor spi interface 22 - 3 spi operation using the spi interface, 8-bit data can be sending and receiving data simultaneously with an external device. a serial clock line synchronizes shifting and sampling of the information on the two serial data lines. the transmission frequency is controlled by making the appropriate bit settings to the sppre register when spi is a master. you can modify its frequency to adjust the baud rate data register value. when spi is a slave, other master supply the clock. when a programmer writes byte data to sptdat register, spi transmit and receive operation will start simultaneously. programming procedure when a byte data is written into the sptdat register, spi starts to transmit if the spcon's spe bit & mstr bit are set. there is a typical programming procedure to operate an spi card. to program the spi modules, follow these basic steps: 1. set baud rate prescaler register (sppre) 2. set spcon & sppin to configure properly the spi module 3. write data 0xff to sptdat 10 times in order to initialize the card 4. set sppin's ncs bit(to '0') to activate the spi card. 5. tx data ? confirm transfer ready flag (redy) to set, and then write data to sptdat. 6. rx data(1): spcon's tagd bit disable = normal mode ? write 0xff to sptdat, then confirm redy to set, and then read data from read buffer 7. rx data(2): spcon's tagd bit enable = tx auto garbage data mode ? confirm redy to set, and then read data from read buffer (then automatically start to transfer) 8. reset sppin's ncs (to '1') to deactivate spi card.
s3c2400 risc microprocessor spi interface 22 - 4 spi transfer format S3C2400X01 supports 4 different format to transfer the data. four waveforms are shown for spiclk. figure 22-2. spi transfer format
s3c2400 risc microprocessor spi interface 22 - 5 steps for transmit by dma 1. the spi is configured as dma mode. 2. dma is configured properly. 3. the spi requests dma service. 4. dma transmits 1byte data to the spi. 5. the spi transmits the data to card. 6. go to step 3 until dma count is 0. 7. the spi is configured as interrupt or polling mode with smod bits. steps for receive by dma 1. the spi is configured as dma start with smod bits and setting tagd bit. 2. dma is configured properly. 3. the spi receives 1byte data from card. 4. the spi requests dma service. 5. dma receives the data from the spi. 6. write data 0xff automatically to sptdat. 7. go to step 4 until dma count is 0. 8. the spi is configured as polling mode with smod bits and clearing tagd bit. 9. if spsta redy flag is set, then read the last byte data. note: total received data = dma tc values + the last data in polling mode(step 9). first dma received data is dummy, so user can neglect that.
s3c2400 risc microprocessor spi interface 22 - 6 spi special registers spi control register(spcon) register address r/w description reset value spcon 0x15900000 r/w spi control register 0x00 spcon bit description initial state spi mode select (smod) [6:5] determines how and by what sptdat is read/written 00 = polling mode, 01 = interrupt mode 10 = dma mode, 11 = reserved 00 prescaler enable (enpre) [4] determines what you want prescaler enable or not(only master) 0 = disable, 1 = enable 0 master/slave select (mstr) [3] determines what mode you want master or slave. 0 = slave, 1 = master note: in slave mode there should be set up time for master to initiate tx / rx. 0 clock polarity select (cpol) [2] determines an active high or active low clock. 0 = active high, 1 = active low 0 clock phase select (cpha) [1] this bit selects one of two fundamentally different transfer formats. 0 = format a, 1 = format b 0 tx auto garbage data mode enable (tagd) [0] this bit decides whether the receiving data only needs or not. when this bit is normal mode and you only want to receive data, you should transmit dummy 0xff data. 0 = normal mode, 1 = tx auto garbage data mode 0
s3c2400 risc microprocessor spi interface 22 - 7 spi status register (spsta) register address r/w description reset value spsta 0x15900004 r spi status register 0x01 spsta bit description initial state reserved [7:3] data collision error flag (dcol) [2] this flag is set if the sptdat is written or the sprdat is read while a transfer is in progress and cleared by reading the spsta with dcol set. 0 = not detect, 1 = collision error detect 0 multi master error flag (mulf) [1] this flag is set if the nss signal goes to active low while the spi is configured as a master, and sppin's enmul bit is multi master errors detect mode. mulf is cleared by reading spsta with mulf set. 0 = not detect, 1 = multi master error detect 0 transfer ready flag (redy) [0] this bit indicates that spt(r)dat is ready to transmit or receive. this flag is automatically resetted by writing data to sptdat. initial value is high. 0 = not ready, 1 = data tx/rx ready 1
s3c2400 risc microprocessor spi interface 22 - 8 spi pin control register (sppin) when the spi system is enabled, the direction of pin is controlled by spcon's mstr bit except /ss pin. the direction and usage of /ss pin is controlled by the sppin's enmul bit when the spi system is a master. otherwise, when the spi system is a slave, /ss pin is always used input for slave select by one master. register address r/w description reset value sppin 0x15900008 r/w spi pin control register 0x02 sppin bit description initial state reserved [7:3] multi master error detect enable (enmul) [2] the /ss pin is used as an input to detect multi master error when the spi system is a master, regardless the sppin's ncs bit. 0 = disable(general purpose) 1 = multi master error detect enable 0 spi card select(ncs) [1] the /ss pin is used as an output to select an spi card when the spi system is a master. if sppin's emul bit is enable, this bit ignores. 0 = card select, 1 = not select 1 master out keep(keep) [0] determines mosi drive or release when 1byte transmit finish(only master) 0 = release, 1 = drive the previous level 0 the spimiso (miso) and spimosi (mosi) data pins are used for transmitting and receiving serial data. when the spi is configured as a master, spimiso (miso) is the master data input line, spimosi (mosi) is the master data output line, and spiclk (sck) is the clock output line. when as a slave, these pins reverse roles. in a multiple- master system, all spiclk (sck) pins are tied together, all spimosi(mosi) pins are tied together, and all spimiso (miso) pins are tied together. only an spi master can experience a multi master error, caused when a second spi device becomes a master and selects this device as if it were a slave. when this type error is detected, the following action are taken immediately. but you must previously set sppin's enmul bit if you want to detect this error. 1. the spcon's mstr bit is forced to 0 to operate slave mode. 2. the spsta's mulf flag is set, and an spi interrupt is generated.
s3c2400 risc microprocessor spi interface 22 - 9 spi baud rate prescaler register (sppre) register address r/w description reset value sppre 0x1590000c r/w spi baud rate prescaler register 0x00 sppre bit description initial state prescaler value [7:0] determines spi clock rate as above equation. baud rate = pclk / 2 / (prescaler value + 1) 0x00 note: baud rate should be less than 25mhz. spi tx data register (sptdat) register address r/w description reset value sptdat 0x15900010 r/w spi tx data register 0x00 sptdat bit description initial state tx data register [7:0] this field contains the data to be transmitted over the spi channel 0x00 spi rx data register(sprdat) register address r/w description reset value sprdat 0x15900014 r spi rx data register 0x00 sprdat bit description initial state rx data register [7:0] this field contains the data to be received over the spi channel 0x00
s3c2400 risc microprocessor spi interface 22 - 10 notes
s3c2400 risc microprocessor electrical data 23- 1 23 electrical data absolute maximum ratings table 23-1. absolute maximum rating symbol parameter rating unit v dd dc supply voltage 3.8 v in dc input voltage 3.3 v input buffer 3.8 v out dc input voltage 3.3 v output buffer 3.8 v i in dc input current 200 ma t stg storage temperature ? 65 to 150 o c recommended operating conditions table 23-2. recommended operating conditions symbol parameter rating unit dc supply voltage for i/o block 3.3v v dd 3.3 0.3 v dd dc supply voltage for analog core 3.3v v dd 3.3 0.5% v in dc input voltage 3.3v input buffer 3.3 0.3 v out dc output voltage 3.3v output buffer 3.3 0.3 v t opr operating temperature commercial 0 to 70 o c
electrical data s3c 2400 risc microprocessor 23- 2 d.c. electrical characteristics the following tables define the dc electrical characteristics for the standard lvcmos i/o buffers. table 23-3. normal i/o pad dc electrical characteristics (v dd = 3.3v 0.3v, t a = -4 0 to 85 c) symbol parameters condition min type max unit v ih high level input voltage v lvcmos interface 2.0 v il low level input voltage v lvcmos interface 0. 8 vt switching threshold 1.4 v vt+ schmitt trigger, positive-going threshold cmos 2.0 v vt- schmitt trigger, negative-going threshold cmos 0.8 i ih high level input current input buffer -10 10 m a input buffer with pull-up v in = v dd 10 33 6 0 i il low level input current input buffer -10 10 m a input buffer with pull-up v in = v ss -60 - 33 - 10 v oh high level output voltage type b8 i oh = -8 ma type b12 i oh = -12 ma 2.4 v v ol low level output voltage type b8 i ol = 8 ma type b12 i ol = 12 ma 0.4 v i ds stop current v in = v ss or v dd tbd (note) m a @25 c i dd operating current tbd (note) ma/mhz note: tbd ? to be determined.
s3c2400 risc microprocessor electrical data 23- 3 table 23-4. usb dc electrical characteristics symbol parameter condition min max unit v ih high level input voltage 2.5 v v il low level input voltage 0.8 v i ih high level input current vin = 3.3v -10 10 m a i il low level input current vin = 0.0v -10 10 m a v oh static output high 15kohm to gnd 2.8 3.6 v v ol static output low 1.5kohm to 3.6v 0.3 v
electrical data s3c 2400 risc microprocessor 23- 4 a.c. electrical characteristics 1/2 v dd 1/2 v dd t xtalcyc note: the clock input from the x tipll pin. figure 23-1. xtipll clock timing t exthigh v ih 1/2 v dd v il v il v ih v ih 1/2 v dd t extlow t extcyc note: the clock input from the extclk pin. figure 23-2. extclk clock input timing
s3c2400 risc microprocessor electrical data 23- 5 tex2ck tex2sck tsck2ck extclk sclk clkout (hclk) figure 23-3. extclk/clkout/sclk in the case that extclk is used without the pll t hc2ck t hc2sck t sck2ck hclk (internal) sclk clkout (hclk) figure 23-4. hclk/clkout/sclk in the case that extclk is used with the pll extclk t mdrh t resw nreset om[3:0] figure 23-5. manual reset and om[3:0] input timing
electrical data s3c 2400 risc microprocessor 23- 6 nreset xtipll or extclk vco output mcu operates by xtipll or extclk clcok. clock disable t osc1 fclk is new frequency. power pll can operate after om[3:2] is latched. pll is configured by s/w first time. vco is adapted to new clock frequency. fclk ... ... ... t rst2ru n figure 23-6. power-on oscillation setting timing
s3c2400 risc microprocessor electrical data 23- 7 xtipll vco output clock disable fclk several slow clocks (xtipll or extclk) stop mode is initiated. t osc2 extclk figure 23-7. stop mode return oscillation setting timing
electrical data s3c 2400 risc microprocessor 23- 8 extclk ngcsx trad noe data addr nbex trcd trod trod trcd tacc trad trad trad trad trad trad trad trad trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh '1' figure 23-8. rom/sram burst read timing(i) (tacs=0, tcos=0, tacc=2, toch=0, tcah=0, pmc=0, st=0, dw=16bit)
s3c2400 risc microprocessor electrical data 23- 9 extclk ngcsx trad noe data addr nbex trcd trod trod trcd trbed trbed tacc trad trad trad trad trad trad trad trad trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh trds trdh figure 23-9. rom/sram burst read timing(ii) (tacs=0, tcos=0, tacc=2, toch=0, tcah=0, pmc=0, st=1, dw=16bit)
electrical data s3c 2400 risc microprocessor 23- 10 extclk ngs noe addr txnbrqs xnbreq txnbrqh xnback 'hz' 'hz' 'hz' txnbackd txnbackd thzd thzd thzd figure 23-10. external bus request in rom/sram cycle (tacs=0, tcos=0, tacc=8, toch=0, tcah=0, pmc=0, st=0)
s3c2400 risc microprocessor electrical data 23- 11 extclk ngs trad tacs noe tcos data addr nbe '1' toch tcah trcd trod trds trdh trod trcd trad tacc figure 23-11. rom/sram read timing (i) (tacs=2,tcos=2, tacc=4, toch=2, tcah=2, pmc=0, st=0)
electrical data s3c 2400 risc microprocessor 23- 12 extclk ngcsx trad tacs noe tcos data addr nbex toch tcah trcd trod trds trdh trod trcd trad tcos toch trbed trbed tacc figure 23-12. rom/sram read timing (ii) (tacs=2, tcos=2, tacc=4, toch=2, tcah=2cycle, pmc=0, st=1)
s3c2400 risc microprocessor electrical data 23- 13 extclk ngcsx trad tacs nwe tcos data addr nbex toch tcah trcd trwd trdd trwd trcd trad tcos toch trwbed trwbed tacc trdd figure 23-13. rom/sram write timing (i) (tacs=2,tcos=2,tacc=4,toch=2, tcah=2, pmc=0, st=0)
electrical data s3c 2400 risc microprocessor 23- 14 extclk ngcsx trad tacs nwe tcos data addr nbex toch tcah trcd trwd trdd trwd trcd trad tcos toch trbed trbed tacc trdd figure 23-14. rom/sram write timing (ii) (tacs=2, tcos=2, tacc=4, toch=2, tcah=2, pmc=0, st=1)
s3c2400 risc microprocessor electrical data 23- 15 extclk ngcsx noe tacc = 6cycle nwait data addr tacs tacs delayed trc note : t he status of nwait is checked at (tacc-1) cycle. sampling nwait figure 23-15. external nwait read timing (tacs=0, tcos=0, tacc=6, toch=0, tcah=0, pmc=0, st=0)
electrical data s3c 2400 risc microprocessor 23- 16 extclk ngcsx nwe data addr trdd trdd tacc >= 2cycle nwait tws twh figure 23-16. external nwait write timing (tacs=0, tcos=0, tacc=4, toch=0, tcah=0, pmc=0, st=0)
s3c2400 risc microprocessor electrical data 23- 17 extclk nrasx tdad trcd ncasx data addr noe tdrd tdrcd tdds tddh tdod tcp tcas tcp tcas tcp tcas tcp tcas tcp tcas tcp tcas tcp tcas tcp tcas figure 23-17. dram (edo) burst read timing (trcd=2, tcas=1, tcp=1, trp=3.5, mt=10, dw = 16bit)
electrical data s3c 2400 risc microprocessor 23- 18 extclk nrasx ncasx addr noe txnbrqs xnbreq xnback txnbrqh txnbackd txnbackd 'hz' 'hz' 'hz' 'hz' thzd thzd thzd thzd txnbrql figure 23-18. external bus request in dram cycle (trcd=3, tcas=2, tcp=1, trp=4.5)
s3c2400 risc microprocessor electrical data 23- 19 extclk nrasx tdad trcd ncasx data addr noe tcp trp tdrd tdrcd tdds tddh tdrcd tdrd tdad tcas tdod tdad tdod figure 23-19. dram(fp) single read timing (trcd=3, tcas=2, tcp=1, trp=4.5, mt=01)
electrical data s3c 2400 risc microprocessor 23- 20 extclk nrasx tdad trcd ncasx data addr noe tcp trp tdrd tdrcd tdds tddh tdrcd tdrd tdad tcas tdod tdad tdod figure 23-20. dram(edo) single read timing (trcd=3, tcas=2, tcp=1, trp=4.5, mt=10)
s3c2400 risc microprocessor electrical data 23- 21 extclk nrasx ncasx addr noe/nwe trp tdrd tdccd tdccd tdrd tchr '1' figure 23-21. dram cbr refresh timing (tchr=4)
electrical data s3c 2400 risc microprocessor 23- 22 extclk nrasx tdad trcd ncasx data addr noe tcp trp tdrd tdrcd tdds tddh tdrcd tdrd tdad tcas tdod tdad tdrcd tcas tdrcd tdrcd tcp tdad tdrcd tcas tdrd tdrcd tdad tdad tdad tdds tddh tdds tddh trcd figure 23-22. dram(edo) page hit-miss read timing (trcd=2, tcas=2, tcp=1, trp=3.5, mt=10)
s3c2400 risc microprocessor electrical data 23- 23 extclk nrasx ncasx addr trp tdrd tdccd tdccd tdrd figure 23-23. dram self refresh timing extclk nrasx tdad trcd ncasx data addr nwe tcp trp tdrd tdwcd tddd tddd tdwcd tdrd tdad tcas tdwd tdad tdwd figure 23-24. dram(fp/edo) single write timing (trcd=3, tcas=2, tcp=1, trp=4.5, mt=01/10)
electrical data s3c 2400 risc microprocessor 23- 24 extclk nrasx tdad trcd ncasx data addr nwe tcp trp tdrd tdwcd tddd tddd tdwcd tdrd tdad tcas tdwd tdad tdwcd tcas tdwcd tdwcd tcp tdad tdwcd tcas tdrd tdwcd tdad tdad tdad tddd tddd trcd figure 23-25. dram(fp/edo) page hit-miss write timing (trcd=2, tcas=2, tcp=1, trp=3.5, mt=01/10)
s3c2400 risc microprocessor electrical data 23- 25 extclk ngcsx trad tacs noe tcos data addr trcd trod trds trdh trad tacc figure 23-26. masked-rom single read timing (tacs=2, tcos=2, tacc=8, pmc=01/10/11) extclk ngcsx trad noe data addr trcd trod trds trdh trad tacc tpac tpac tpac tpac trad trad trad trad trds trdh trds trdh trds trdh trds trdh figure 23-27. masked-rom consecutive read timing (tacs=0, tcos=0, tacc=3, tpac=2, pmc=01/10/11)
electrical data s3c 2400 risc microprocessor 23- 26 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsds tsdh scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' trcd tsbed tcl figure 23-28. sdram single burst read timing (trp=2, trcd=2, tcl=2, dw=16bit)
s3c2400 risc microprocessor electrical data 23- 27 sclk nsras nscas addr/ba nbex txnbrqh txnbrqs scke a10/ap ngcsx nwe '1' xnbreq xnback extclk txnbackd txnbackd 'hz' 'hz' 'hz' 'hz' 'hz' 'hz' 'hz' 'hz' 'hz' thzd thzd thzd thzd thzd thzd thzd thzd thzd txnbrql figure 23-29. external bus request in sdram timing (trp=2, trcd=2, tcl=2)
electrical data s3c 2400 risc microprocessor 23- 28 sclk nsras tsad nscas data addr/ba nbex tsrd scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tscsd tsrd 'hz' '1' tswd figure 23-30. sdram mrs timing
s3c2400 risc microprocessor electrical data 23- 29 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsds tsdh scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tsad trcd tscsd tsrd tscsd tsad tsad tsbed tcl figure 23-31. sdram single read timing(i) (trp=2, trcd=2, tcl=2)
electrical data s3c 2400 risc microprocessor 23- 30 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsds tsdh scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tsad trcd tscsd tsrd tscsd tsad tsad tsbed tcl figure 23-32. sdram single read timing(ii) (trp=2, trcd=2, tcl=3)
s3c2400 risc microprocessor electrical data 23- 31 sclk nsras tsad trp nscas data addr/ba nbex tsrd scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tscsd tsrd '1' '1' 'hz' trc note: before executing auto/self refresh command, all banks must be idle state. figure 23-33. sdram auto refresh timing (trp=2, trc=4)
electrical data s3c 2400 risc microprocessor 23- 32 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsds tsdh scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' trcd tsbed tcl tcl tcl figure 23-34. sdram page hit-miss read timing (trp=2, trcd=2, tcl=2)
s3c2400 risc microprocessor electrical data 23- 33 sclk nsras tsad trp nscas data addr/ba nbex tsrd scke a10/ap ngcsx tscsd nwe tsad tscd tswd tsad tscsd tsrd '1' '1' 'hz' trc tcked 'hz' '1' '1' '1' '1' '1' tcked note: before executing auto/self refresh command, all banks must be idle state. figure 23-35. sdram self refresh timing (trp=2, trc=4)
electrical data s3c 2400 risc microprocessor 23- 34 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsdd tsdd scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' tsad tsad trcd tscsd tsrd tscsd tsad tsad tsbed figure 23-36. sdram single write timing (trp=2, trcd=2)
s3c2400 risc microprocessor electrical data 23- 35 sclk nsras tsad trp nscas data addr/ba nbex tsrd tsdd tsdd scke a10/ap ngcsx tscsd nwe tsad tscd tswd '1' trcd tsbed figure 23-37. sdram page hit-miss write timing (trp=2, trcd=2, tcl=2)
electrical data s3c 2400 risc microprocessor 23- 36 xsclk txrs txrs tcadl tcadh txad xnxdreq xnxdack read write min. 3mclk figure 23-38. external dma timing (handshake, single transfer) first line check & data timing vframe vm vline vclk vframe vm vline vclk vd[7:0] expanded view t1 t2 tl2c tc2dhold tc2dsetup tcwidth figure 23-39. stn lcd controller timing
s3c2400 risc microprocessor electrical data 23- 37 vsync hsync vden tf2hsetup tf2hhold tvspw tvbpd tvfpd hsync vclk vd vden lend tl2csetup tvclkh tvclk tvclkl tvdhold tvdsetup tve2hold tle2chold tlewidth figure 23-40. tft lcd controller timing
electrical data s3c 2400 risc microprocessor 23- 38 mmcclk mmccm mmcda tcmds tcmdh tdats tdath figure 23-41. mmc interface receive timing spiclk spimiso spimosi (slave) tmisos tmisoh tmosis tmosih figure 23-42. spi interface receive timing
s3c2400 risc microprocessor electrical data 23- 39 table 23-5. clock timing constants (v ddp = 3.3v, v ddi = 1.8v, t a = 25 c, max/min = typ 30%) parameter symbol min typ max unit crystal clock input frequency f xtal 6 ? 20 mhz crystal clock input cycle time t xtalcyc 50 ? 166.7 ns external clock input frequency f ext 1 ? 66 mhz external clock input cycle time t extcyc 15.1 ? 1000 ns external clock input low level pulse width t extlow 5 ? ? ns external clock to clkout (without pll) t ex2ck ? 14 ? ns external clock to sclk (without pll) t ex2sclk ? 9.1 ? ns hclk(internal) to clkout (with pll) t hc2ck ? 7.7 ? ns hclk(internal) to sclk (with pll) t hc2sclk ? 2.8 ? ns sclk to ckout t sclk2ck ? 4.9 ? ns external clock input high level pulse width t exthigh 5 ? ? ns mode reset hold time t mdrh 3.0 ? ? ns reset assert time after clock stabilization t resw 4 ? ? xtipll or extclk power-on oscillation setting time t osc1 ? ? 4096 xtipll or extclk stop mode return oscillation setting time t osc2 ? ? 4096 xtipll or extclk the interval before cpu runs after nreset is released. t rst2run ? 7 ? xtipll or extclk
electrical data s3c 2400 risc microprocessor 23- 40 table 23-6. rom/sram bus timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ max unit rom/sram address delay t rad ? 13 ? ns rom/sram chip select delay t rcd ? 8 ? ns rom/sram output enable delay t rod ? 7 ? ns rom/sram read data setup time. t rds ? 1 ? ns rom/sram read data hold time. t rdh ? 5 ? ns rom/sram byte enable delay t rbed ? 8 ? ns rom/sram write byte enable delay t rwbed ? 8 ? ns rom/sram output data delay t rdd ? 8 ? ns rom/sram external wait setup time t ws ? 1 ? ns rom/sram external wait hold time t wh ? 5 ? ns rom/sram write enable delay t rwd ? 9 ? ns
s3c2400 risc microprocessor electrical data 23- 41 table 23-7. clock timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ max unit dram address delay t dad ? 9 ? ns dram row active delay t drd ? 14 ? ns dram read column active delay t drcd ? 15 ? ns dram output enable delay t dod ? 14 ? ns dram read data setup time t dds ? 1 ? ns dram read data hold time t ddh ? 5 ? ns dram write cas active delay t dwcd ? 15 ? ns dram cbr cas active delay t dccd ? 9 ? ns dram write enable delay t dwd ? 15 ? ns dram output data delay t ddd ? 16 ? ns table 23-8. memory interface timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ max unit sdram address delay t sad ? 5 ? ns sdram chip select delay t scsd ? 4 ? ns sdram row active delay t srd ? 4 ? ns sdram column active delay t scd ? 4 ? ns sdram byte enable delay t sbed ? 4 ? ns sdram write enable delay t swd ? 4 ? ns sdram read data setup time t sds ? 4 ? ns sdram read data hold time t sdh ? 0 ? ns sdram output data delay t sdd ? 5 ? ns sdram clock eable delay t cked ? 5 ? ns
electrical data s3c 2400 risc microprocessor 23- 42 table 23-9. external bus request timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ. max unit external bus request setup time t xnbrqs ? 2 ? ns external bus request hold time t xnbrqh ? 5 ? ns external bus ack delay t xnbackd ? 15 ? ns hz delay t hzd ? 6 ? ns table 23-10. dma controller module signal timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ. max unit external request setup t xrs ? 9.3 ? ns access to ack delay when low transition t cadl ? 6.8 ? ns access to ack delay when high transition t cadh ? 6.6 ? ns external request delay t xad 2 ? ? mclk
s3c2400 risc microprocessor electrical data 23- 43 table 23-11. stn lcd controller module signal timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ max units vframe setup to vline falling edge t1 16 ? ? phclk (note) vframe hold from vline falling edge t2 16 ? ? phclk vline falling edge to vclk rising edge tl2c 16 ? ? phclk vd setup to vclk falling edge tc2dsetup 2 ? ? phclk vd hold from vclk falling edge tc2dhold 2 ? ? phclk vclk period tcwidth 4 ? ? phclk note: hclk period table 23-12. tft lcd controller module signal timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ max units vertical sync pulse width tvspw vspw + 1 ? ? phclk (note1) vertical back porch delay tvbpd vbpd+1 ? ? phclk vertical front porch dealy tvfpd vfpd+1 ? ? phclk vclk pulse width tvclk 1 ? ? pvclk (note2) vclk pulse width high tvclkh 0.5 ? ? pvclk vclk pulse width low tvclkl 0.5 ? ? pvclk hsync setup to vclk falling edge tl2csetup 0.5 ? ? pvclk vden set up to vclk falling edge tde2csetup 0.5 ? ? pvclk vden hold from vclk falling edge tde2chold 0.5 ? ? pvclk vd setup to vclk falling edge tvd2csetup 0.5 ? ? pvclk vd hold from vclk falling edge tvd2chold 0.5 ? ? pvclk lend width tlewidth 1 ? pvclk lend hold from vclk rising edge tle2chold 3 ? ? ns vsync setup to hsync falling edge tf2hsetup hspw + 1 ? ? pvclk vsync hold from hsync falling edge tf2hhold hbpd + hfpd + hozval + 3 ? ? pvclk notes: 1. hsync period 2. vclk period
electrical data s3c 2400 risc microprocessor 23- 44 table 23-13. iis controller module signal timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ. max unit iislrck delay time t lrck 0.5 ? 5.7 ns iisdo delay time t sdo 0.4 ? 2.5 ns iisdi input setup time t sdis 7.9 ? ? ns iisdi input hold time t sdih 0.3 ? ? ns codec clock frequency t codec 1/16 ? 1 f iis_block table 23-14. iic bus controller module signal timing (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ. max unit scl clock frequency f scl ? ? std. 100 fast 400 khz scl high level pulse width t sclhigh std. 4.0 fast 0.6 ? ? m s scl low level pulse width t scllow std. 4.7 fast 1.3 ? ? m s bus free time between stop and start t buf std. 4.7 fast 1.3 ? ? m s start hold time t starts std. 4.0 fast 0.6 ? ? m s sda hold time t sdah std. 0 fast 0 ? std. - fast 0.9 m s sda setup time t sdas std. 250 fast 100 ? ? ns stop setup time t stoph std. 4.0 fast 0.6 ? ? m s note: std. means standard mode and fast means fast mode.
s3c2400 risc microprocessor electrical data 23- 45 table 23-15. mmc interface transmit/receive timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ. max unit cmd receive data input setup time t cmds ? 9.1 ? ns cmd receive data input hold time t cmdh ? 0.1 ? ns dat receive data input setup time t dats ? 8.8 ? ns dat receive data input hold time t dath ? 0.1 ? ns table 23-16. spi interface transmit/receive timing constants (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol min typ. max unit miso receive data input setup time t misos ? 9.4 ? ns miso receive data input hold time t misoh ? 0.1 ? ns mosi(slave) receive data input setup time t mosis ? 0.1 ? ns mosi(slave) receive data input hold time t mosih ? 0.8 ? ns
electrical data s3c 2400 risc microprocessor 23- 46 table 23-17. usb electrical specifications (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol condition min max unit supply current suspend device iccs 10 a leakage current hi-z state input leakage ilo 0v < vin < 3.3v -10 10 a input levels differential input sensitivity vdi | (d+) ? (d-) | 0.2 v differential common mode range vcm includes vdi range 0.8 2.5 single ended receiver threshold vse 0.8 2.0 output levels static output low vol rl of 1.5kohm to 3.6v 0.3 v static output high voh rl of 15kohm to gnd 2.8 3.6 capacitance transceiver capacitance cin pin to gnd 20 pf table 23-18. usb full speed output buffer electrical characteristics (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol condition min max unit driver characteristics transition time rise time fall time tr tf cl = 50pf cl = 50pf 4.0 4.0 2.0 2.0 ns rise/fall time matching trfm (tr / tf ) 90 110 % output signal crossover voltage vcrs 1.3 2.0 v drive output resistance zdrv steady state drive 28 43 ohm
s3c2400 risc microprocessor electrical data 23- 47 table 23-19. usb low speed output buffer electrical characteristics (v dd = 1.8 v 0.15 v, t a = 0 to 70 c, v ext = 3.3v 0.3v) parameter symbol condition min max unit driver characteristics transition time rising time falling time tr tf cl = 50pf cl = 350pf cl = 50pf cl = 350pf 75 75 300 300 ns rise/fall time matching trfm (tr / tf ) 80 120 % output signal crossover voltage vcrs 1.3 2.0 v
electrical data s3c 2400 risc microprocessor 23- 48 notes
s3c2400 risc microprocessor mechanical data 24- 1 24 mechanical data package dimensions 208-lqfp-2828 #208 28.00 0.20 30.00 0.30 28.00 0.20 30.60 0.30 0.10max 0.127 + 0.10 - 0.05 0-8 note : dimensions are in millimeters. #1 0.50 0.20 0.10 0.05 1.40 0.10 1.60max 0.50 (1.25) + 0.10 - 0.05 0.20 0.08max figure 24-1. 208-lqfp- 2828 package dimension
mechanical data s3c2400 risc microprocessor 24- 2 figure 24-2. 208-fbga-12.0x12.0 package dimension 1
s3c2400 risc microprocessor mechanical data 24- 3 figure 24-3. 208-fbga-12.0x12.0 package dimension 2
mechanical data s3c2400 risc microprocessor 24- 4 figure 24-4. 208-fbga-15.0x15.0 package dimension 1
s3c2400 risc microprocessor mechanical data 24- 5 figure 24-5. 208-fbga-15.0x15.0 package dimension 2
mechanical data s3c2400 risc microprocessor 24- 6 notes

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